Question

我不熟悉在modelsim 10.4b中使用UVM。我试图检查我的类是否正在编译，但我收到以下编译错误。此外，如果有人能指出我的UVM执行流程，这将是非常有帮助的。我搜索了在线资源。

class fifo_trans_item extends uvm_sequence_item;

    rand bit [15:0] data_in;
    rand bit push;
    rand bit pop;
    rand bit w_en;
    rand bit r_en;

endclass

这是我得到的错误。如果这是与工具相关的问题，请将我重定向到论坛以询问此问题。

Loading project MIPS
# reading modelsim.ini
# Loading project UVM_tb
# UVM Details: design does not contain any  UVM components, UVM debugging is disabled, or an  unknown questa_uvm_pkg has been loaded.
# Compile of sequence.sv failed with 2 errors.

** Error: (vlog-13069) /afs/asu.edu/users/s/m/u/smukerji/sequence.sv(1): near "uvm_sequence_item": syntax error, unexpected IDENTIFIER.
** Error: /afs/asu.edu/users/s/m/u/smukerji/sequence.sv(1): Error in class extension specification.

Answer 1

你需要

import uvm_pkg::*;
`include "uvm_macros.svh"

在引用UVM基类库和宏的每个文件中

在Modelsim 10.4b中编译和模拟UVM TB

1 个答案: