Question

以下代码在Verilog中实现了Delta-sigma DAC，来自Xilinx应用笔记，我想编写等效的VHDL代码。我对Verilog一无所知，而且我是VHDL的初学者所以我不得不做出很多猜测，可能是初学者错误（下面的代码）。我不确定翻译是否正确，有人可以帮忙吗？

原始Verilog

`timescale 100 ps / 10 ps
`define MSBI 7

module dac(DACout, DACin, Clk, Reset);
output DACout;
reg DACout;
input [`MSBI:0] DACin;
input Clk;
input Reset;

reg [`MSBI+2:0] DeltaAdder;
reg [`MSBI+2:0] SigmaAdder;
reg [`MSBI+2:0] SigmaLatch;
reg [`MSBI+2:0] DeltaB;

always @(SigmaLatch) DeltaB = {SigmaLatch[`MSBI+2], SigmaLatch[`MSBI+2]} << (`MSBI+1);
always @(DACin or DeltaB) DeltaAdder = DACin + DeltaB;
always @(DeltaAdder or SigmaLatch) SigmaAdder = DeltaAdder + SigmaLatch;
always @(posedge Clk or posedge Reset)
begin
    if(Reset)
    begin
        SigmaLatch <= #1 1'bl << (`MSBI+1);
        DACout <= #1 1'b0;
    end
    else
    begin
        SigmaLatch <== #1 SigmaAdder;
        DACout <= #1 SigmaLatch[`MSBI+2];
    end
end
endmodule

我在VHDL中的尝试：

entity audio is
    generic(
        width  : integer := 8
    );
    port(
        reset  : in    std_logic;
        clock  : in    std_logic;
        dacin  : in    std_logic_vector(width-1 downto 0);
        dacout : out   std_logic
    );
end entity;

architecture behavioral of audio is
    signal deltaadder    : std_logic_vector(width+2 downto 0);
    signal sigmaadder    : std_logic_vector(width+2 downto 0);
    signal sigmalatch    : std_logic_vector(width+2 downto 0);
    signal deltafeedback : std_logic_vector(width+2 downto 0);
begin
    deltafeedback <= (sigmalatch(width+2), sigmalatch(width+2), others => '0');
    deltaadder <= dacin + deltafeedback;
    sigmaadder <= deltaadder + sigmalatch;

    process(clock, reset)
    begin
        if (reset = '1') then
            sigmalatch <= ('1', others => '0');
            dacout <= '0';
        elsif rising_edge(clock) then
            sigmalatch <= sigmaadder;
            dacout <= sigmalatch(width+2);
        end if;
    end process;
end architecture;

Answer 1

看起来你正在使用ieee.std_logic_unsigned（或_arith）或两者兼而有之。

Please don't do that。请改用ieee.numeric_std.all。

我的Verilog相当不存在，所以我忘记了Verilog默认使用有符号或无符号算术......但无论哪种算法，都要将所有数字信号转换为signed或unsigned类型以匹配

你的重置条款可能想要读取如下内容：

sigmalatch <= (width+1 => '1', others => '0');

并且deltafeedback更新类似于：

deltafeedback(width+2 downto width+1) <= sigmalatch(width+2) & sigmalatch(width+2);
deltafeedback(width downto 0) <= (others => '0');

最后，为了匹配Verilog，我认为您的width通用应该被称为MSBI并设置为7，（或将您的所有width+2更改为width+1 s符合您对width通用）的意图

Answer 2

如果您只是对VHDL中的Delta-sigma DAC感兴趣，您可以查看我发布到alt.sources的实现（请选择“原始消息”，保存到文件并运行“unshar”on得到消息来源。

WOJTEK

从Verilog到VHDL的Delta-sigma DAC

2 个答案: