运行50 ns
#KERNEL:在10 ns时停止在delta:5000 #KERNEL:错误:KERNEL_0160 Delta计数溢出。使用asim的-i参数或匹配条目增加迭代限制 模拟偏好。
#Error:模拟过程中发生致命错误。
我哪里错了?
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity funct is
port(x: in std_logic_vector (2 downto 1);
y: out std_logic);
end funct;
architecture funct of funct is
signal r, s, q : std_logic_vector(2 downto 0) := "000";
begin
process
begin
wait on x, q;
r(2) <= not(q(0)) or (not(q(1)) and x(2) and not(x(1)));
r(1) <= q(2) and not(x(2));
r(0) <= not(q(1)) and q(0) and x(1);
s(2) <= q(1) and x(2);
s(1) <= not(q(2)) and q(0) and not(x(2));
s(0) <= not(q(2)) and not(q(1)) and not(q(0)) and x(2);
end process;
y <= q(2) and not(q(1)) and q(0);
process
begin
wait on r, s;
q(0) <= s(0) or (not(r(0)) and q(0));
q(1) <= s(1) or (not(r(1)) and q(1));
q(2) <= s(2) or (not(r(2)) and q(2));
end process;
end funct;
答案 0 :(得分:3)
这两个过程以循环方式相互触发:
x
最初更改时,会触发第一个进程r
和s
由第一个流程wait
,q
,wait
中使用了什么所以第一个,第二个,第一个......进程的执行继续而不增加时间,但随着增量计数器增量,直到达到增量计数器限制,你得到你看到的错误。
要解决此问题,您需要纠正组合逻辑以避免内部循环。
此外,等待信号的过程类似于:
process is
begin
...
wait on {signals};
end process;
通常写成:
process ({signals}) is
begin
...
end process;
如果在此过程中编写了纯粹的组合逻辑,那么您实际上可以跳过创建过程,因此您的代码可以写成:
r(2) <= not(q(0)) or (not(q(1)) and x(2) and not(x(1)));
r(1) <= q(2) and not(x(2));
r(0) <= not(q(1)) and q(0) and x(1);
s(2) <= q(1) and x(2);
s(1) <= not(q(2)) and q(0) and not(x(2));
s(0) <= not(q(2)) and not(q(1)) and not(q(0)) and x(2);
y <= q(2) and not(q(1)) and q(0);
q(0) <= s(0) or (not(r(0)) and q(0));
q(1) <= s(1) or (not(r(1)) and q(1));
q(2) <= s(2) or (not(r(2)) and q(2));
以这种方式编写代码,清楚地揭示了从q(0)
到r(0)
到q(0)
的组合循环。