Question

我使用以下代码作为向上计数器的第一位。我已经制作了必要的端口映射，我没有语法错误。虽然我的模拟不起作用。

 entity ZeroBit is
        Port ( inbit0 : in  STD_LOGIC;
                   Load : in  STD_LOGIC;
                   Q0 : out  STD_LOGIC;
                   En : in  STD_LOGIC;
                      reset : in STD_LOGIC;
                      Clk : in STD_LOGIC;
                   UpDown : in  STD_LOGIC);
        end ZeroBit;

        architecture Behavioral of ZeroBit is

        component D_FlipFlop 
            Port ( Din : in  STD_LOGIC;
                   En : in  STD_LOGIC;
                   Q : out  STD_LOGIC;
                      reset : in STD_LOGIC;
                   Clk : in  STD_LOGIC);
        end component;

        component andGate 
            Port ( A : in  STD_LOGIC;
                   B : in  STD_LOGIC;
                   F : out  STD_LOGIC);
        end component;

        component orGate 
            Port ( A : in  STD_LOGIC;
                   B : in  STD_LOGIC;
                   F : out  STD_LOGIC);
        end component;

        component notGate 
            Port ( in0 : in  STD_LOGIC;
                   out0 : out  STD_LOGIC);
        end component;

        component Mux4x1 
            Port ( C0 : in  STD_LOGIC;
                   C1 : in  STD_LOGIC;
                   X0 : in  STD_LOGIC;
                   X1 : in  STD_LOGIC;
                   X2 : in  STD_LOGIC;
                   X3 : in  STD_LOGIC;
                   M : out  STD_LOGIC);
        end component;

        signal muxout, inmux0, inmux1, orout, andout0, andout1, notUpDown : std_logic;

        begin

        FF0 : D_FlipFlop
            port map ( Din => muxout,
                          En => '1',
                          Q => inmux0,
                          reset => reset,
                          Clk => Clk );

        Mux0 : Mux4x1
            port map( C0 => orout,
                         C1 => Load,
                         X0 => inmux0,
                         X1 => inmux1,
                         X2 => inbit0,
                         X3 => inbit0,
                         M => muxout);

        notG : notGate
            port map( in0 => UpDown,
                         out0 => notUpDown);

        and0 : andGate
            port map( A => En,
                         B => notUpDown,
                         F => andOut0);

        and1 : andGate
            port map( A => En,
                         B => UpDown,
                         F => andOut1);
    orG : orGate
    port map( A => andOut0,
                 B => andOut1,
                 F => orout);

        Q0 <= inmux0;

    end Behavioral;

我附上了模拟的屏幕截图。

Answer 1

查看代码，inmux1上没有驱动程序。默认情况下，这将驱动'U'，这将传播。

vhdl中的模拟错误

1 个答案: