Question

更新：新的time_engine流程

out_s <= conv_std_logic_vector(sec1,6);
out_m <= conv_std_logic_vector(min1,6);
out_h <= conv_std_logic_vector(hour1,5);

time_engine: process(clk_base)
begin
if rising_edge(clk_base) then
  if (reset='1') then 
    sec1 <= 0;
    min1 <= 0;
    hour1 <= 0; 
    newday <='0';
else
    if(set_time='1') then
            sec1 <= sec_pre;
            min1 <= min_pre;
            hour1 <= hour_pre;
    else
        if (sec_enable= '1') then
            sec1 <= sec1+1;
            if(sec1 = 59) then
                sec1<=0;
                min1 <= min1 + 1;
                if(min1 = 59) then
                    hour1 <= hour1 + 1;
                    min1  <= 0;
                    if(hour1 = 23) then
                        hour1  <= 0;
                        newday <= '1';
                    else
                        newday <= '0';
                    end if;
                end if;
            end if;
        end if; 
     end if;
   end if;  
end if;
end process time_engine;

更新：更改了非门控时钟的进程 Glitch visible at port out_ss

我添加了上面的图片。现在有一个时钟启用1s-clk，一切都与基本clk_in同步。端口out_ss等在clk_in的上升沿更新。我认为由于硬件延迟我可能会得到“错误”值（毛刺值），但这不是问题。相反，端口仍然会获得所有毛刺转换。注意毛刺时间比clk_in的周期短得多，那么如果没有clk的上升沿，如何将该值写入输出端口？（实际上它似乎是在上升沿发生之前更新的，因为正确的值出现在每次正好1s后，应该如此。）这让我感到困惑。

Glitch in Seconds (4th line from below)

自从我使用Xilinx / iSim完成后合成仿真已经有很长一段时间了，所以我认为我一般都做错了。我实际上正在开发一个比这个更复杂的项目，但是在后合成模拟中有很多故障，所以我尝试了一个简单的实时时钟，但我仍然在秒之间得到相同的故障（当然对于其他港口也是如此）。无论基准时钟或模拟有多慢。但这只是一个简单的反击......为什么？我该如何防止这种情况？

这两个组件（是的，有未使用的信号和端口）：

library IEEE;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity prescaler is
port(
    clk_in  : in std_logic; 
    stop        : in std_logic;
    clk_out     : out std_logic 
     );
end prescaler;

architecture Behavioral of prescaler is
signal count : integer :=1;
    signal clk_1Hz : std_logic :='0';
    begin

clk_divide: process(clk_in, stop)
begin
    if (stop ='1') then
    count <=0;
    else
         if rising_edge(clk_in) then
            count <=count+1;
            if(count = 10) then -- 100MHz 50000000 -> 1:5 für tb
                clk_1Hz <='1';
                count <=1;
            else
                clk_1Hz <='0';
            end if;
        end if;
    end if;
end process clk_divide;

clk_out <= clk_1Hz;
end Behavioral;

library IEEE;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity gen_time is
port(
    clk     : in std_logic;

    in_s        : in std_logic_vector(5 downto 0);
    in_m        : in std_logic_vector(5 downto 0); 
    in_h        : in std_logic_vector(4 downto 0);  

    set_time    : in std_logic;
    reset       : in std_logic;

    ref_m   : out std_logic_vector(5 downto 0); 
    ref_h   : out std_logic_vector(4 downto 0);

    out_s   : out std_logic_vector(5 downto 0);
    out_m   : out std_logic_vector(5 downto 0); 
   out_h    : out std_logic_vector(4 downto 0);

    clk_day  : out std_logic
     );
end gen_time;

architecture Behavioral of gen_time is

signal sec_pre,min_pre              : integer range 0 to 59 :=0;
signal sec1,min1                    : integer range 0 to 59 :=0;
signal hour1, hour_pre              : integer range 0 to 23 :=0;

signal newday                       : std_logic := '0'; 

begin

    sec_pre <= conv_integer(in_s);
    min_pre <= conv_integer(in_m);
    hour_pre <= conv_integer(in_h);

    ref_m <= conv_std_logic_vector(min1,6);
    ref_h <= conv_std_logic_vector(hour1,5);

    clk_day <= newday;

time_engine: process( clk_base, reset, set_time ) 
begin
if rising_edge(clk_base) then
    if (reset='1') then 
        sec1 <= 0;
        min1 <= 0;
        hour1 <= 0; 
        newday <='0';
    else
         if(set_time='1') then 
            sec1 <= sec_pre;
            min1 <= min_pre;
            hour1 <= hour_pre;
    else
        if (sec_enable= '1') then
            sec1 <= sec1+1;     
            if(sec1 = 59) then
                sec1<=0;
                min1 <= min1 + 1;
                if(min1 = 59) then
                    hour1 <= hour1 + 1;
                    min1  <= 0;
                        if(hour1 = 23) then
                            hour1  <= 0;
                            newday <= NOT newday;
                        end if;
                    end if;
                end if;
            end if; 
        end if;
   end if;  
end if;
out_s <= conv_std_logic_vector(sec1,6);
out_m <= conv_std_logic_vector(min1,6);
out_h <= conv_std_logic_vector(hour1,5);

end process time_engine;
end Behavioral;

测试平台：只提供时钟

简单的VHDL手表 - 后期合成iSim毛刺

0 个答案: