Question

在Isim波形窗口中，我的内部信号和输出显示为绿色并初始化，但即使它们也被初始化，我的所有输入都显示为“UU”。我只是尝试在两个输入中的任何一个为1时添加1.代码合成良好而没有警告。有什么想法吗？

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;

entity scoreboard2 is
    Port ( clk : in  STD_LOGIC;
           T1 : in  STD_LOGIC;
           T2 : in  STD_LOGIC;
           Output : out  STD_LOGIC_VECTOR (3 downto 0));
end scoreboard2;

architecture Behavioral of scoreboard2 is
signal output_temp: STD_LOGIC_VECTOR(3 downto 0) := "0000";
signal score1,score2: unsigned(1 downto 0) := "00";
signal score3: unsigned(3 downto 0):= "0000";

begin
    proc: process(T1,T2,clk)
    begin
        if(rising_edge(clk)) then
            if(T1 = '1') then
                score1 <= score1 + 1;
            end if;
            if(T2 = '1') then
                score2 <= score2 + 1;
            end if;
        end if;
    end process proc;

score3 <= score1 & score2;
output_temp <= STD_LOGIC_VECTOR(score3);
Output <= output_temp;

end Behavioral;



LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;


ENTITY test6 IS
END test6;

ARCHITECTURE behavior OF test6 IS 

    COMPONENT scoreboard2
    PORT(
         clk : IN  std_logic;
         T1 : IN  std_logic;
         T2 : IN  std_logic;
         Output : OUT  std_logic_vector(3 downto 0)
        );
    END COMPONENT;


   --Inputs
   signal clk : std_logic := '1';
   signal T1 : std_logic := '1';
   signal T2 : std_logic := '1';

    --Outputs
   signal Output : std_logic_vector(3 downto 0) := "0000";
    signal output_temp: STD_LOGIC_VECTOR(3 downto 0) := "0000";
    signal score1,score2: unsigned(1 downto 0) := "00";
    signal score3: unsigned(3 downto 0):= "0000";

   constant clk_period : time := 10 ns;

BEGIN

   uut: scoreboard2 PORT MAP (
          clk => clk,
          T1 => T1,
          T2 => T2,
          Output => Output
        );

   clk_process :process
   begin
        clk <= '0';
        wait for clk_period/2;
        clk <= '1';
        wait for clk_period/2;
   end process;


   stim_proc: process
   begin        
        wait for 100 ns;
        T1 <= '1';
      wait;
   end process;

END;

Answer 1

我没有Isim，但有些模拟器允许您使用具有未连接输入的端口运行顶级设计。它通常与进行交互式模拟（运行，停止，步进，强制输入等）的能力同义。

ise_tutorial_ug695.pdf的第5章，2011年3月1日（第13.1节）说你需要一个测试平台，我没有所有文件来确定是否强制执行。

对于测试平台：

library ieee;
use ieee.std_logic_1164.all;

entity scoreboard_tb is
end entity;

architecture test of scoreboard_tb is
    signal clk:     std_logic := '0';
    signal T1:      std_logic := '0';
    signal T2:      std_logic := '0';
    signal RESULT:  std_logic_vector(3 downto 0);
begin

UNDER_TEST:
    entity work.scoreboard2 
        port map (
            clk => clk,
            T1 => T1,
            T2 => T2,
            Output => RESULT
        );
CLOCK:
    process 
    begin
        if Now > 340 ns then     -- simulation stops with no signal events 
            wait;
        end if;
        clk <= not clk; 
        wait for 20 ns;      
    end process;
STIMULUS:
    process
    begin
        wait for 40 ns;
        T1 <= '1';
        wait for 40 ns;
        T2 <= '1';
        wait for 40 ns;
        T1 <= '0';
        T2 <= '0';
        wait for 40 ns;
        T2 <= '1';
        wait for 40 ns;
        T2 <= '0';
        T1 <= '1';
        wait for 40 ns;
        T1 <= '0';
        wait;

    end process;

end architecture;

ghdl产生：

enter image description here

对于你的记分牌2实体/架构对分析未变。

Answer 2

我也没有Isim。软波本身可能效果不佳。如果在Isim中有波形编辑器或类似的东西，请使用它而不是测试台。然后再次模拟您的项目。希望这会有所帮助：）

Isim Wave Window中的VHDL编码

2 个答案: