Question

我有一个简单的VHDL设计和测试平台，不能产生预期的输出。 ISim显示＆＃39; U＆＃39;对于所有输出，直到＆＃39;运行＆＃39;达到了状态（myState =＆＃39; 1＆＃39;）。然后他们显示0和X值。第一个PROCESS块应将所有输出设置为＆＃39; 0＆＃39;当ENABLE是＆＃39; 0＆＃39;。测试平台切换ENABLE 0-1-0以确保事件触发过程，但输出保持在＆＃39; U＆＃39;。是设计，测试还是两者都有问题？

VHDL

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity TestHarness1 is
port (
    ADAT_WDCLK : in std_logic;
    ADAT_BCLK: in std_logic;
    ADAT_OUT12: in std_logic;
    ENABLE: in std_logic;

    PCM_FS : out std_logic;
    PCM_CLK : out std_logic;
    PCM_DIN : out std_logic
);
end TestHarness1;

architecture Behavioral of TestHarness1 is
    --type state is (STOPPED, RUNNING);
    signal tmp : std_logic;
    signal myState : std_logic;
begin
    PCM_DIN <= tmp; 

    -- State management process
    process (ENABLE, ADAT_WDCLK) begin -- Eval on input changes
        if (ENABLE = '0') then 
            myState <= '0'; --STOPPED;
            PCM_FS <= '0'; -- All outputs muted
            PCM_CLK <= '0';
            tmp <= '0';
        else
            if (myState = '0' and rising_edge(ADAT_WDCLK)) then
                -- Move to running state only at start of a frame
                myState <= '1'; --RUNNING;
            end if;
        end if;
    end process;

    -- Output process
    process (ADAT_WDCLK, ADAT_BCLK, myState) variable counter: integer := 0; begin
        -- Only do something if we are in running state, process above
        -- sets outputs when stopped.
        if (myState = '1') then

            -- Pass the clocks through, inverting the bit clock
            PCM_FS <= ADAT_WDCLK;
            PCM_CLK <= not ADAT_BCLK;

            -- Generate fixed bit pattern data '11000101'
            if rising_edge(ADAT_WDCLK) then
                -- This would happen naturally since there are 4 bytes per word clock
                counter := 0;
            end if;
            if falling_edge(ADAT_WDCLK) then
                -- This would happen naturally since there are 4 bytes per word clock
                counter := 0;
            end if;
            if rising_edge(ADAT_BCLK) then -- Change data state only on falling edge of output PCM_CLK
                if counter = 0 or counter = 1 or counter = 5 or counter = 7 then
                    tmp <= '1';
                else
                    tmp <= '0';
                end if;
                if (counter = 7) then
                    counter := 0;       -- Reset counter
                else
                    counter := counter + 1; -- Just inc counter
                end if;

            end if;
        end if;
    end process;
end Behavioral;

试验台

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

ENTITY TH1TestBench3 IS
END TH1TestBench3;

ARCHITECTURE behavior OF TH1TestBench3 IS 

    -- Component Declaration for the Unit Under Test (UUT)

    COMPONENT TestHarness1
    PORT(
         ADAT_WDCLK : IN  std_logic;
         ADAT_BCLK : IN  std_logic;
         ADAT_OUT12 : IN  std_logic;
         ENABLE : IN  std_logic;
         PCM_FS : OUT  std_logic;
         PCM_CLK : OUT  std_logic;
         PCM_DIN : OUT  std_logic
        );
    END COMPONENT;


   --Inputs
   signal ADAT_WDCLK : std_logic := '0';
   signal ADAT_BCLK : std_logic := '0';
   signal ADAT_OUT12 : std_logic := '0';
   signal ENABLE : std_logic := '0';

    --Outputs
   signal PCM_FS : std_logic;
   signal PCM_CLK : std_logic;
   signal PCM_DIN : std_logic;

   -- Clock period definitions. Note WDCLK is defined in terms of the bit clock
    -- to insure they are exactly in sync.
   constant ADAT_BCLK_period : time := 326 ns; -- About 3.072MHz (https://www.sensorsone.com/frequency-to-period-calculator/)
   constant ADAT_WDCLK_period : time := ADAT_BCLK_period * 64; -- 48KHz

BEGIN

    -- Instantiate the Unit Under Test (UUT)
   uut: TestHarness1 PORT MAP (
          ADAT_WDCLK => ADAT_WDCLK,
          ADAT_BCLK => ADAT_BCLK,
          ADAT_OUT12 => ADAT_OUT12,
          ENABLE => ENABLE,
          PCM_FS => PCM_FS,
          PCM_CLK => PCM_CLK,
          PCM_DIN => PCM_DIN
        );


   -- Clock process definitions
   ADAT_WDCLK_process :process
   begin
        ADAT_WDCLK <= '0';
        wait for ADAT_WDCLK_period/2;
        ADAT_WDCLK <= '1';
        wait for ADAT_WDCLK_period/2;
   end process;

   ADAT_BCLK_process :process
   begin
        ADAT_BCLK <= '1';
        wait for ADAT_BCLK_period/2;
        ADAT_BCLK <= '0';
        wait for ADAT_BCLK_period/2;
   end process;


   -- Stimulus process
   stim_proc: process
   begin        
      -- hold reset state for 100 ns.
      wait for 100 ns;  
        ENABLE <= '1';
        wait for 100 ns;
        ENABLE <= '0';
        wait for 7500 ns;
        ENABLE <= '1';


      wait for ADAT_WDCLK_period*10;

      -- insert stimulus here 

      wait;
   end process;

END;

ISim在模拟的早期显示ENABLE脉冲，但输出仍然是“U＆＃39;直到WCLK的上升沿，ENABLE = 1。然后他们开始改变（按照设计），但他们显示了一些X值。

修改后的VHDL

作为参考，这里是修改后的VHDL，它解决了模拟输出中U和X的问题。但是，PCM_DIN输出存在功能问题......似乎是延迟一个（BCLK）周期。我希望它是＆＃39; 1＆＃39;一旦ADAT_WDCLK在ENABLE之后第一次变高。但它没有进入＆＃39; 1＆＃39;直到BLCK循环。

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity TestHarness1 is
port (
    ADAT_WDCLK : in std_logic;
    ADAT_BCLK: in std_logic;
    ADAT_OUT12: in std_logic;
    ENABLE: in std_logic;

    PCM_FS : out std_logic;
    PCM_CLK : out std_logic;
    PCM_DIN : out std_logic
);
end TestHarness1;

architecture Behavioral of TestHarness1 is
    --type state is (STOPPED, RUNNING);
    signal tmp : std_logic;
    signal myState : std_logic;
begin
    PCM_DIN <= tmp; 

    -- State management process
    process (ENABLE, ADAT_WDCLK) begin -- Eval on input changes
        if (ENABLE = '0') then 
            myState <= '0'; --STOPPED;
        else
            if (myState = '0' and rising_edge(ADAT_WDCLK)) then
                -- Move to running state only at start of a frame
                myState <= '1'; --RUNNING;
            end if;
        end if;
    end process;

    -- Output process
    process (ADAT_WDCLK, ADAT_BCLK, myState) variable counter: integer := 0; begin
        -- Only do something if we are in running state
        if (myState = '0') then
            PCM_FS <= '0'; -- All outputs muted
            PCM_CLK <= '0';
            tmp <= '0';
        elsif (myState = '1') then
            -- Pass the clocks through, inverting the bit clock
            PCM_FS <= ADAT_WDCLK;
            PCM_CLK <= not ADAT_BCLK;

            if rising_edge(ADAT_BCLK) then -- Generate fixed serial bit pattern
                if counter = 0 or counter = 1 or counter = 5 or counter = 7 then
                    tmp <= '1';
                else
                    tmp <= '0';
                end if;
                if (counter = 7) then
                    counter := 0;       -- Reset counter
                else
                    counter := counter + 1; -- Just inc counter
                end if;

            end if;
        end if;
    end process;

end Behavioral;

以上的ISim（包括内部myState信号）...为什么PCM_DIN延迟了一个BCLK周期？

Answer 1

关于＆＃39; X＆＃39;您正在看到的（强制未知）值：

您正在从多个进程中驱动信号PCM_FS，PCM_CLK和tmp，这会导致模拟器无法解析被驱动的值。您需要修复此问题，以便它们仅从一个进程驱动，或在不使用时驱动'Z'。

关于＆＃39; U＆＃39;值存在，因为您没有信号的初始值。一旦您第一次写入信号（启用后），它们将首次分配。

ISim显示所有输出的U.

1 个答案: