Question

我是VHDL的新手，今天是我向教授提交项目的截止日期，所以请耐心等待我哈哈。我编写了这段代码，它将两个4位无符号数相乘，并使用一个8位全加器来执行此操作（这是教授要求的）。这是我的源代码：

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity Atividade2 is
port(a,b: in std_logic_vector(0 to 7); clk,rst: in std_logic; prod: out std_logic_vector(0 to 7) := "00000000");
end Atividade2; 
architecture Behavioral of Atividade2 is

component somador_8bit
port(a,b: in std_logic_vector(0 to 7); ci: in std_logic; soma: out std_logic_vector(0 to 7); co: out std_logic);
end component;

signal result: std_logic_vector(0 to 7);
signal reg2: std_logic_vector(0 to 7);
signal reg3: integer range 0 to 15;
signal reg4: std_logic_vector(0 to 7);
signal cont: integer range 0 to 15 := 0;

begin

SOMA: somador_8bit port map(reg2,a,'0',result,open);
reg4 <= b;
process(clk)
begin
if rising_edge(clk) then
reg3 <= to_integer(unsigned(reg4));
if(cont < reg3) then
reg2 <= result;
cont <= cont + 1;
end if;
end if;

end process;
prod <= result;

end Behavioral;

这是测试台代码：

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
USE IEEE.STD_LOGIC_TEXTIO.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE STD.TEXTIO.ALL;

ENTITY atv2wf IS
END atv2wf;

ARCHITECTURE testbench_arch OF atv2wf IS
FILE RESULTS: TEXT OPEN WRITE_MODE IS "results.txt";

COMPONENT Atividade2
    PORT (
        a : In std_logic_vector (0 To 7);
        b : In std_logic_vector (0 To 7);
        clk : In std_logic;
        rst : In std_logic;
        prod : Out std_logic_vector (0 To 7)
    );
END COMPONENT;

SIGNAL a : std_logic_vector (0 To 7) := "00000000";
SIGNAL b : std_logic_vector (0 To 7) := "00000000";
SIGNAL clk : std_logic := '0';
SIGNAL rst : std_logic := '0';
SIGNAL prod : std_logic_vector (0 To 7) := "00000000";

constant PERIOD : time := 20 us;
constant DUTY_CYCLE : real := 0.5;
constant OFFSET : time := 100 us;

BEGIN
    UUT : Atividade2
    PORT MAP (
        a => a,
        b => b,
        clk => clk,
        rst => rst,
        prod => prod
    );

    PROCESS    -- clock process for clk
    BEGIN
        WAIT for OFFSET;
        CLOCK_LOOP : LOOP
            clk <= '0';
            WAIT FOR (PERIOD - (PERIOD * DUTY_CYCLE));
            clk <= '1';
            WAIT FOR (PERIOD * DUTY_CYCLE);
        END LOOP CLOCK_LOOP;
    END PROCESS;

    PROCESS
        BEGIN
            -- -------------  Current Time:  109us
            WAIT FOR 109 us;
            rst <= '1';
            a <= "00000111";
            b <= "00000010";
            -- -------------------------------------
            -- -------------  Current Time:  129us
            WAIT FOR 20 us;
            rst <= '0';
            -- -------------------------------------
            WAIT FOR 891 us;

        END PROCESS;

END testbench_arch;

这是我的RTL视图。一切似乎都设置好了，接线很好，RTL电路似乎没问题，但我得到的只是 prod 输出的“U”。任何人都可以保存meee ?? RTL View

永远在我的输出上获得“U”

0 个答案: