Question

我正在用VHDL编写Matrix Transpose的代码我在每个时钟周期以行主要和矩阵的一个元素为输入，并且我以列主格式存储数据之后我以coloumn主格式元素发送数据元素每个时钟周期到输出。代码如下所示是正确模拟，但后合成结果不对，任何人都可以帮助如何合成代码以获得正确的结果

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.ALL;

entity Matrix_Trans_Sysgen is
generic(n: integer :=3);
port (my_clk : in std_logic;
my_ce : in std_logic;
input_matrix : in std_logic_vector(5 downto 0);
output_matrix : out std_logic_vector(5 downto 0)
);
end Matrix_Trans_Sysgen;

architecture Behavioral of Matrix_Trans_Sysgen is

type t1 is array (natural range<>) of std_logic_vector(5 downto 0);

signal a : t1((n*n)-1 downto 0) :=(others => (others =>'0'));

signal output_there : std_logic :='0';

signal x : integer range 0 to 2*n :=0;
signal y : integer range 0 to 2*n :=0;
signal z : integer range 0 to 2*n*n :=0;

begin

----- Process to take all input_matrix into array
process(my_clk,input_matrix,x,y)
begin

if(x < n) then

    if(y < n) then
       if(rising_edge(my_clk)) then 
          a(y*n+x) <= input_matrix;
          y <= y+1;
       end if;
    else
      x<=x+1;
      y<=0;
    end if;
  else
    output_there <= '1';

end if;
end process;


----- Process to send all output elements through port
process(my_clk,z,output_there)
begin

if (output_there = '1') then

    if(z < n*n) then


      if(rising_edge(my_clk)) then


         output_matrix <= a(z);
         z<=z+1;

      end if;

    end if;

end if;

end process;

end Behavioral;

谢谢和问候

的Teja

Answer 1

使用通常的时钟进程模板重写它。也就是说，用

“if rising_edge(clk) then ...”

过程中最外层。综合工具寻找这个结构并正确处理它;其他形式的过程可能会混淆这些工具。

在综合后仿真中出错

1 个答案: