Question

我在Xilinx Vivado中有一个模块，无法运行后合成模拟并跟随以下错误：

Starting static elaboration

ERROR: [VRFC 10-380] binding entity insertion_sort does not have generic array_length 
ERROR: [VRFC 10-718] formal port <sort_in> does not exist in entity <insertion_sort>.  Please compare the definition of block <insertion_sort> to its component declaration and its instantion to detect the mismatch. 
ERROR: [VRFC 10-718] formal port <sorted_out> does not exist in entity <insertion_sort>.  Please compare the definition of block <insertion_sort> to its component declaration and its instantion to detect the mismatch. 
ERROR: [XSIM 43-3321] Static elaboration of top level VHDL design unit sort_tb in library work failed.

但行为模拟和合成本身运行正常。

INFO: [Common 17-83] Releasing license: Synthesis
21 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
synth_design completed successfully

这是模块的描述

entity insertion_sort is
    generic(
        array_length:integer:=9
    );
    Port (
        clk: in std_logic;
        reset: in std_logic;
        start_sorting: in std_logic;
        sort_in: in array_of_ints (0 to array_length-1);
        sorted_out: out array_of_ints(0 to array_length-1);
        sort_ready: out std_logic
    );

end insertion_sort;

array_of_ints在包中定义为

package array_def is
    type array_of_ints is array (natural range<>) of integer range -200 to 200 ;

end package;

在测试台中实例化模块

entity sort_tb is
    generic(
     tb_length: integer:=9
    );
    --Port ( );
end;

architecture test_sorting of sort_tb is

    constant clock_cycle: time:=20 ns;
    signal start, ready, tclk, rst: std_logic;
    signal test_array_in, test_array_out: array_of_ints(0 to tb_length-1);
    signal  run_num: positive:=1;
    component insertion_sort
        generic ( array_length: integer);
        port(
            clk: in std_logic;
            reset: in std_logic;
            start_sorting: in std_logic;
            sort_in: in array_of_ints (0 to array_length-1);
            sorted_out: out array_of_ints(0 to array_length-1);
        sort_ready: out std_logic);

    end component;

    begin
    DUT: insertion_sort 
    generic map( array_length=>tb_length)
    port map (clk=>tclk,
        reset=>rst,
        start_sorting=>start,
        sort_in=>test_array_in,
        sorted_out=>test_array_out,
    sort_ready=>ready  );

希望我提供足够的信息。提前感谢您的帮助

编辑：按照Paebbels的要求，由vivado创建的新文件中的实体说明。

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity insertion_sort is
  port (
    clk : in STD_LOGIC;
    reset : in STD_LOGIC;
    start_sorting : in STD_LOGIC;
    \sort_in[0]\ : in STD_LOGIC_VECTOR ( 8 downto 0 );
    \sort_in[1]\ : in STD_LOGIC_VECTOR ( 8 downto 0 );
    \sort_in[2]\ : in STD_LOGIC_VECTOR ( 8 downto 0 );
    \sort_in[3]\ : in STD_LOGIC_VECTOR ( 8 downto 0 );
    \sort_in[4]\ : in STD_LOGIC_VECTOR ( 8 downto 0 );
    \sort_in[5]\ : in STD_LOGIC_VECTOR ( 8 downto 0 );
    \sort_in[6]\ : in STD_LOGIC_VECTOR ( 8 downto 0 );
    \sort_in[7]\ : in STD_LOGIC_VECTOR ( 8 downto 0 );
    \sort_in[8]\ : in STD_LOGIC_VECTOR ( 8 downto 0 );
    \sorted_out[0]\ : out STD_LOGIC_VECTOR ( 8 downto 0 );
    \sorted_out[1]\ : out STD_LOGIC_VECTOR ( 8 downto 0 );
    \sorted_out[2]\ : out STD_LOGIC_VECTOR ( 8 downto 0 );
    \sorted_out[3]\ : out STD_LOGIC_VECTOR ( 8 downto 0 );
    \sorted_out[4]\ : out STD_LOGIC_VECTOR ( 8 downto 0 );
    \sorted_out[5]\ : out STD_LOGIC_VECTOR ( 8 downto 0 );
    \sorted_out[6]\ : out STD_LOGIC_VECTOR ( 8 downto 0 );
    \sorted_out[7]\ : out STD_LOGIC_VECTOR ( 8 downto 0 );
    \sorted_out[8]\ : out STD_LOGIC_VECTOR ( 8 downto 0 );
    sort_ready : out STD_LOGIC
  );
  attribute NotValidForBitStream : boolean;
  attribute NotValidForBitStream of insertion_sort : entity is true;
  attribute array_length : integer;
  attribute array_length of insertion_sort : entity is 9;
end insertion_sort;

Vivado：虽然行为运行

0 个答案: