Question

我正在尝试在verilog中进行定点分割，并且遇到两个与未声明的端口（r2和c2）相关的错误。我不知道为什么会这样，因为在c和q它的工作原理。你可以帮帮我吗？感谢。

module tema1(a,b,q,c,r);

    input[7:0] a;  
    input[7:0] b; 

    output[15:0] q; 
    reg[15:0] q;
    output[7:0] r2;
    output[7:0] c;
    output[7:0] c2;
    output[7:0] r;
reg[7:0] r2;
    reg[7:0] c;
    reg[7:0] c2;
    reg[7:0] r;

    always @(*)
        begin


        c = 8'b00000000;
        r = a;
        c2 = 8'b00000000;

        repeat (30)
                    begin
                        if (r >= b )
                            begin
                        c = c + 1;
                        r = r - b;
                            end
                    end

        $display("c=%d", c);
        $display("r=%d",r);



                r = r * 10;
                r2 = r;
                repeat (30)
                    begin
                        if (r2 >= b  )
                            begin
                            c2 = c2 + 1;
                        r2= r2 - b;
                            end
                    q[8:7]=c2;

                    end


                r = r * 10;
                r2 = r;
                repeat (30)
                    begin
                        if (r2 >= b  )
                            begin
                            c2 = c2 + 1;
                        r2= r2 - b;
                            end
                        q[7:6]=c2;

                    end


                r = r * 10;
                r2 = r;
                repeat (30)
                    begin
                        if (r2 >= b  )
                            begin
                            c2 = c2 + 1;
                        r2= r2 - b;
                            end
                        q[6:5]=c2;

                    end


                r = r * 10;
                r2 = r;
                repeat (30)
                    begin
                        if (r2 >= b  )
                            begin
                            c2 = c2 + 1;
                        r2= r2 - b;
                            end
                        q[5:4]=c2;

                    end


                r = r * 10;
                r2 = r;
                repeat (30)
                    begin
                        if (r2 >= b  )
                            begin
                            c2 = c2 + 1;
                        r2= r2 - b;
                            end
                        q[4:3]=c2;

                    end

                r = r * 10;
                r2 = r;
                repeat (30)
                    begin
                        if (r2 >= b  )
                            begin
                            c2 = c2 + 1;
                        r2= r2 - b;
                            end
                         q[3:2]=c2;

                    end


                r = r * 10;
                r2 = r;
                repeat (30)
                    begin
                        if (r2 >= b  )
                            begin
                            c2 = c2 + 1;
                        r2= r2 - b;
                            end
                         q[2:1]=c2;

                    end


                r = r * 10;
                r2 = r;
                repeat (30)
                    begin
                        if (r2 >= b  )
                            begin
                            c2 = c2 + 1;
                        r2= r2 - b;
                            end
                    q[1:0]=c2;

                    end






end

endmodule

Answer 1

您收到此错误是因为您将r2和c2声明为输出，但它们未出现在端口列表中。您使用的语法来自Verilog-1995，您可能需要定义最多3次的端口（端口列表中的1个位置，方向和数据类型）。请使用Verilog-2001（现在是SystemVerilog）的更新语法

module tema1(
        input[7:0] a,b,
        output reg [15:0] q,
        output reg [7:0] c, r
        );
// internal 
        reg[7:0] c2, r2;

未声明的端口verilog错误

1 个答案: