verilog端口映射语法错误

Question

Error-[SE] Syntax error
      Following verilog source has syntax error :
      "design.sv", 5: token is '['
        mux4x1 inst1(.sel[0](k), .sel[1](j), .I[0](q), I[1](0), .I[2](1), 
      .I[3](qb), .y(W1));
                          ^

1 error

Answer 1

您无法将信号映射到总线的各个位。相反，您需要将信号的串联映射到整个总线上：

mux4x1 inst1(.sel({k, j}), .I({q, 2'b01, qb}), .y(W1));