错误（10278）：TrafficLight.v（5）处的Verilog HDL端口声明错误：输入端口“t”无法声明类型为“<a variable="" data="" type,="" e.g.="" reg="">&#34;

Question

verilog error while I try to implement a traffic light system with six states I wanted to display lights red, green, yellow on the led display of ALTERA DE2 board

code is as below

module TrafficLight(clk, t, out);
    input clk, t;
    output out;
    localparam s0=3'b000, s1=3'b001, s2=3'b010, s3=3'b011, s4=3'b100, s5=3'b101;
    reg[2:0] state, next_state, t;

    always@(posedge clk)
    begin
        state = next_state;
        t = t - 1;
    end

    always@(t or state)
         begin
         case(state)
              3'b000:
                    if(t < 5)
                         next_state = s0;
                    else
                    begin
                         next_state = s1;
                         assign out [5:0] = 6'b100001;
                    end
              3'b001:
                    if(t < 1)
                         next_state = s1;
                    else
                    begin
                         next_state = s2;
                         assign out [5:0] = 6'b010001;
                    end
              3'b010:
                    if(t < 1)
                         next_state = s2;
                    else
                    begin
                         next_state = s3;
                         assign out [5:0] = 6'b001001;
                    end
              3'b011:
                    if(t < 5)
                         next_state = s3;
                    else
                    begin
                         next_state = s4;
                         assign out [5:0] = 6'b001100;
                    end
              3'b100:
                    if(t < 1)
                         next_state = s4;
                    else
                    begin
                         next_state = s5;
                         assign out [5:0] = 6'b001010;
                    end
              3'b101:
                    if(t < 1)
                         next_state = s0;
                    else
                    begin
                         next_state = s5;
                         assign out [5:0] = 6'b001001;
                    end
                endcase
            end
    endmodule

What is wrong with this code can anyone fix it?

Answer 1

在Verilog中，输入不能是reg，正如错误消息所示。请勿通过更改此行声明t为reg：

reg[2:0] state, next_state, t;

到此：

reg[2:0] state, next_state;