Question

所以我有这个RS232通信链路的接收器代码，我应该发送8位，1个起始位“0”和一个停止位“1”，没有奇偶校验位，我试过用这些代码大多数方式，但模拟从来没有正常工作，即使有些人告诉我我的问题是测试平台而不是代码，但它从未在FPGA实现上工作，我发送的第一个信号总是错误的，因为之后的任何信号是正确的

这是下面的代码

    entity Rs232Rxd is

        port( Reset, Clock16x, Rxd: in std_logic; 

        DataOut1: out std_logic_vector (7 downto 0));

        end Rs232Rxd;

 architecture Rs232Rxd_Arch of Rs232Rxd is 

attribute enum_encoding: string;

-- state definitions

type stateType is (stIdle, stData, stStop, stRxdCompleted);

attribute enum_encoding of statetype: type is "00 01 11 10";

signal iReset : std_logic;

signal iRxd1, iRxd2 : std_logic := '1';

signal presState: stateType; 

signal nextState: stateType;

signal iClock1xEnable, iClock1x, iEnableDataOut: std_logic :='0' ; 

signal iClockDiv: std_logic_vector (3 downto 0) := (others=>'0') ;

signal iDataOut1, iShiftRegister: std_logic_vector (7 downto 0):= (others=>'0');

signal iNoBitsReceived: std_logic_vector (3 downto 0):= (others=>'0') ;

begin

process (Clock16x) begin

        if rising_edge(Clock16x) then 

            if Reset = '1' or iReset = '1' then

                iRxd1 <= '1';

                iRxd2 <= '1';

                iClock1xEnable <= '0'; 

                iClockDiv <= (others=>'0');

            else

                iRxd1 <= Rxd; 

                iRxd2 <= iRxd1;

            end if;

            if iRxd1 = '0' and iRxd2 = '1' then 

                iClock1xEnable <= '1';

            end if;

            if iClock1xEnable = '1' then

                iClockDiv <= iClockDiv + '1';

        end if;

        end if;

end process;


iClock1x <= iClockDiv(3);

process (iClock1xEnable, iClock1x) 

begin

    if iClock1xEnable = '0' then 

            iNoBitsReceived <= (others=>'0');

            presState <= stIdle;

    elsif rising_edge(iClock1x) then

                iNoBitsReceived <= iNoBitsReceived + '1';

                presState <= nextState;

                if iEnableDataOut = '1' then

                iDataOut1 <= iShiftRegister;

                --iShiftRegister <= (others=>'0');

                    else

                        iShiftRegister <= Rxd & iShiftRegister(7 downto 1);

            end if;
        end if;

end process;

DataOut1 <= iDataOut1;

process (presState, iClock1xEnable, iNoBitsReceived) 

begin

-- signal defaults 

iReset <= '0';

iEnableDataOut <= '0';


case presState is

    when stIdle =>

    if iClock1xEnable = '1' then

    nextState <= stData;

    else
        nextState <= stIdle;

    end if; 

    when stData =>

    if iNoBitsReceived = "1000" then

    iEnableDataOut <= '1';

    nextState <= stStop;

    else

    iEnableDataOut <= '0'; 

    nextState <= stData;

    end if; 
    when stStop =>   

    nextState <= stRxdCompleted; 

    when stRxdCompleted =>

    iReset <= '1';

    nextState <= stIdle;

    end case; 

end process;

end Rs232Rxd_Arch;

Answer 1

您的问题不会出现Minimal Complete and Verifiable Example。如果不编写测试平台就不能重复这个问题，而且你的问题缺乏特异性（这里使用的'信号'和'错误'是不精确的）。

有一些观察结果。

停止位后跟一个连续字符的起始位不会留下状态stRxdCompleted的空间。当iClock1xEnable变为无效时，iNoBitsReceived也不会设置为全0，这意味着采样点不是由连续字符的起始位的下降沿决定的：

这是一个大写'A'，紧接着是小写'a'，停止位紧跟第二个字符的起始位（这是合法的）。

在第一个字符中，您会看到起始位被计为字符位之一。

当启用无效时，您还会看到位计数器未复位，这将导致采样点漂移（最终可能会导致采样错误，具体取决于时钟差异或传输失真以及缺少异步采样点复位）。 / p>

在第一个字符的最后一个数据位中，您还看到presState是stStop，但第二个字符是正确的。仔细观察一下，我们看到第一个字符的起始位出现在stData期间，第二个字符的出现位没有出现。

当iClock1x停止时，存在状态数和状态转换的基本问题。

你不需要状态机，你有一个名为iNoBitsReceived的计数器可以存储所有状态，如果ishiftregister足够长以容纳启动（并且可能停止）位，你还应该检测帧错误。

在没有单独的状态机的情况下将操作绑定到特定计数，并在空闲时清除位计数器：

给我们一些有点复杂性的东西：

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity Rs232Rxd is
    port ( 
        Reset, 
        Clock16x, 
        Rxd:        in  std_logic; 
        DataOut1:   out std_logic_vector (7 downto 0)
    );
end entity Rs232Rxd;

architecture foo of Rs232Rxd is
    signal rxd1:                std_logic;
    signal rxd2:                std_logic;
    signal baudctr:             unsigned (3 downto 0);
    signal ctr16x:              unsigned (3 downto 0);
    signal enab1xstart:         std_logic;
    signal enable1x:            std_logic;
    signal ninthbit:            std_logic;
    signal sampleenab:          std_logic;
    signal shiftregister:       std_logic_vector(7 downto 0);

begin
CLOCK_DOMAIN:
    process (clock16x)
    begin
        if rising_edge(clock16x) then
            rxd1 <= rxd;
            rxd2 <= rxd1;
        end if;
    end process;

    enab1xstart <= not rxd1 and rxd2 and not enable1x;

ENABLE_1X:
    process (clock16x, reset)
    begin
        if reset = '1' then
            enable1x <= '0';
        elsif rising_edge(clock16x) then
            if enab1xstart = '1' then
                enable1x <= '1';
            elsif ninthbit = '1' then
                enable1x <= '0';
            end if;
        end if;
    end process;

SAMPLE_COUNTER:
    process (clock16x, reset, ninthbit)
    begin
        if reset = '1' or ninthbit = '1' then
            ctr16x <= (others => '0');   -- for simulation
        elsif rising_edge(clock16x) then
            if enab1xstart = '1' or enable1x = '1' then
                ctr16x <= ctr16x + 1;
            end if;
        end if;
    end process;

    sampleenab <= not ctr16x(3) and ctr16x(2) and ctr16x(1) and ctr16x(0);

BAUD_COUNTER:
    process (clock16x, reset)
    begin
        if reset = '1' then
            baudctr <= (others => '0');
        elsif rising_edge(clock16x) and sampleenab = '1' then
            if baudctr = 8 then
                baudctr <= (others => '0');
            else
                baudctr <= baudctr + 1;
            end if;
        end if;
    end process;

NINTH_BIT:  -- one clock16x period long, after baudctr changes 
    process (clock16x, reset)
    begin
        if reset = '1' then
            ninthbit <= '0';
        elsif rising_edge(clock16x) then
            ninthbit <= sampleenab and     baudctr(3) and not baudctr(2) and 
                                       not baudctr(1) and not baudctr(0);
        end if;
    end process;

SHIFT_REG:
    process (clock16x, reset)
    begin
        if reset = '1' then
            shiftregister <= (others => '0'); -- for pretty waveforms
        elsif rising_edge(clock16x) and sampleenab = '1' then
            shiftregister <= rxd2 & shiftregister(7 downto 1);
        end if;
    end process;

OUTREG:
    process (clock16x, reset)
    begin
        if reset = '1' then
            dataout1 <= (others => '0');
        elsif rising_edge(clock16x) and ninthbit = '1' then
            dataout1 <= shiftregister;
        end if;
    end process;

end architecture;

VHDL基本标识符不区分大小写，名称不是特别有启发性。上述两种波形的格式表示名称更改方便。

如果将移位寄存器的长度延长一或两，则可以在停止位期间检测帧错误。更改移位寄存器的长度需要切换移位寄存器输出以写入数据输出。

请注意，此架构编写为使用包numeric_std而不是Synopsys包std_logic_arith。您也没有在实体声明之前提供上下文子句。

该架构还可以产生并使用16x时钟，而不是产生1x时钟。

在找到原始架构中正确问题的更改量似乎压倒性之后写的。（如有疑问，请重新开始。）

使用了这个测试平台：

library ieee;
use ieee.std_logic_1164.all;

entity rs232rxd_tb is
end entity;

architecture foo of rs232rxd_tb is
    signal reset:       std_logic := '0';
    signal clock16x:    std_logic := '0';
    signal rxd:         std_logic := '1'; 
    signal dataout1:    std_logic_vector (7 downto 0);
begin
DUT:
    entity work.rs232rxd
        port map (
            reset => reset,
            clock16x => clock16x,
            rxd => rxd,
            dataout1 => dataout1
        );
CLOCK:
    process
    begin
        wait for 3.255 us;    -- 16X clock divided by 2, 9600 baud 104.16 us
        clock16x <= not clock16x;
        if now > 2.30 ms then
            wait;
        end if;
    end process;

   STIMULI:
    process
    begin
        wait for 6.51 us;
        reset <= '1';
        wait for 13.02 us;
        reset <= '0';
        wait for 13.02 us;
        wait for 40 us;
        rxd <= '0';
        wait for 104.16 us;  -- start bit
        rxd <= '1';
        wait for 104.16 us;  -- first data bit, bit 0 =  '1'
        rxd <= '0';
        wait for 104.16 us;  -- second data bit, bit 1 = '0'
        rxd <= '0';
        wait for 104.16 us;  -- third data bit, bit 2 = '0';
        wait for 104.16 us;  -- fourth data bit, bit 3 = '0';
        wait for 104.16 us;  -- fifth data bit, bit 4 = '0';
        wait for 104.16 us;  -- sixth data bit, bit 5 = '0';
        rxd <= '1';
        wait for 104.16 us;  -- seventh data bit, bit 6 = '1';
        rxd <= '0'; 
        wait for 104.16 us;  -- eigth data bit, bit 7 = '0';
        rxd <= '1'; 
        wait for 104.16 us;  -- stop bit ( = '1')
        --wait for 104.16 us;  -- idle 
        rxd <= '0';
        wait for 104.16 us;  -- start bit
        rxd <= '1';
        wait for 104.16 us;  -- first data bit, bit 0 =  '1'
        rxd <= '0';
        wait for 104.16 us;  -- second data bit, bit 1 = '0'
        rxd <= '0';
        wait for 104.16 us;  -- third data bit, bit 2 = '0';
        wait for 104.16 us;  -- fourth data bit, bit 3 = '0';
        wait for 104.16 us;  -- fifth data bit, bit 4 = '0';
        rxd <= '1';
        wait for 104.16 us;  -- sixth data bit, bit 5 = '1';
        wait for 104.16 us;  -- seventh data bit, bit 6 = '1';
        rxd <= '0'; 
        wait for 104.16 us;  -- eigth data bit, bit 7 = '0';
        rxd <= '1'; 
        wait for 104.16 us;  -- stop bit ( = '1')
        wait;
    end process;
end architecture;

您可以看到新架构具有所有相同的基本元素，尽管时钟流程元素位于单独的流程语句中。

没有状态机进程。

该架构可通过分离移位寄存器的分离输入（用于奇偶校验，两个停止位，7个数据位等）扩展到全功能UART接收器。奇偶校验可以连续执行。

VHDL RS232接收器与Xilinx ISE无法正常工作

1 个答案: