Question

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_SIGNED.all;
use std.env.all;
USE IEEE.STD_LOGIC_TEXTIO.ALL;
USE STD.TEXTIO.ALL;


ENTITY tb_top IS
END tb_top;

ARCHITECTURE behavior OF tb_top IS 

-- Component Declaration for the Unit Under Test (UUT)

COMPONENT c4b
PORT(
     clock : IN  std_logic;
     reset : IN  std_logic;
     count : OUT  std_logic_vector(3 downto 0)
    );
END COMPONENT;


--Inputs
signal clock : std_logic := '0';
signal reset : std_logic := '0';

--Outputs
signal count : STD_LOGIC_vector(3 downto 0) := "0000";

-- Clock period definitions
constant period : time := 100 ns;

-- Opening the file in write mode
file myfile : TEXT open write_mode is "fileio.txt";

BEGIN
    -- Instantiate the Unit Under Test (UUT)
    uut: c4b PORT MAP (
        clock => clock,
        reset => reset,
        count => count
    );

clock_process :process      --providing clock to the counter
begin
    clock <= '1';
    wait for period/2;
    clock <= '0';
    wait for period/2;
end process;

write_process: process
    variable abd: LINE;
    --variable val1: integer;
    begin
        --val1 := CONV_INTEGER(count);          --saw this in another program. even they converted a std_logic_vector to integer. didn't work!
        loop                                                --tried the infinite loop to check for the value 1111,
            if (count = "1111") then                --so that as soon as count reaches the value 1111, 
                finish (0);                             --it would stop, because i only need to write one entire sequence of the cycle to the file!!
            else
                write (abd, count);                 
                writeline (myfile, abd);            
            end if;
        end loop;
    end process;

-- Stimulus process
stim_process: process
begin
    reset <= '0';                                   --because it only works when reset is 0!
    wait for 100 ns;
    if (count = "1111") then                        --the value is written to the text file in a continuous loop,
        finish (0);                                     --which makes he file size go to as much as 1 GB
    end if;                                             --thus to stop it at exactly one cycle!
end process;
END;

所以，基本上我想要做的就是让计数器从0000开始计数1111，然后将整个序列写入文本文件。但我只想写一个周期。因此，我添加了一个循环来检查相同的内容。在上面的代码中，我无法正确模拟测试平台。当我不包含代码的write_process部分时，模拟工作完美，只给我一个周期！（没有write_process picture no 1的模拟器结果）。但是当我尝试使用write_process时，它不仅不会模拟（添加write_process后的模拟器结果）picture no 2，它还会连续写入UUUU文件，直到我关闭ISim，文件大小变为至少几百MB！请帮忙！

Answer 1

如果没有c4b的实体/架构，没有人可以复制您的错误，但它是可见的。

请注意，写入过程没有敏感度列表，也没有等待语句和循环语句，除非提供外部刺激，否则不会退出 - if (count = "1111") then ...

在stim_process和write_process中使用完成似乎并不合适，不保证执行顺序可以丢失最后一次写入（如果你解决了写入过程缺陷）。

您有四个未使用的use子句（numeric_std，std_logic_arith，std_logic_signed，std_logic_textio，VHDL -2008）。

所以，基本上我想要做的就是让计数器从0000开始计数1111，然后将整个序列写入文本文件。

在您的模拟完成之前，您的代码中没有任何内容可以清空输出。在驱动写入过程的事件中写入一行到文件textio.txt。

为c4b添加模型：

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std_unsigned.all;

entity c4b is
    port (
        clock:  in  std_logic;
        reset:  in  std_logic;
        count:  out std_logic_vector(3 downto 0)
    );
end entity;

architecture foo of c4b is 
begin
    process (clock, reset)
    begin
        if reset = '1' then
            count <= (others => '0');
        elsif rising_edge (clock) then
            count <= count + 1;
        end if;
    end process;
end architecture;

删除未使用的使用条款（非必要）：

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
-- USE IEEE.NUMERIC_STD.ALL;
--  IEEE.STD_LOGIC_ARITH.all;
-- use IEEE.STD_LOGIC_SIGNED.all;
use std.env.all;
-- USE IEEE.STD_LOGIC_TEXTIO.ALL;
USE STD.TEXTIO.ALL;

将write_process更改为无限循环：

-- write_process: process
--     variable abd: LINE;
--     --variable val1: integer;
--     begin
--         --val1 := CONV_INTEGER(count);          --saw this in another program. even they converted a std_logic_vector to integer. didn't work!
--         loop                                                --tried the infinite loop to check for the value 1111,
--             if (count = "1111") then                --so that as soon as count reaches the value 1111,
--                 finish (0);                             --it would stop, because i only need to write one entire sequence of the cycle to the file!!
--             else
--                 write (abd, count);
--                 writeline (myfile, abd);
--             end if;
--         end loop;
--     end process;

write_process: 
    process
        variable abd: LINE;
    begin
        wait on count;
        wait for 100 ns;
        write (abd, count);                 
        writeline (myfile, abd);   
        if count = "1111" then
            finish (0);
        elsif IS_X(count) then
            report "count contains a metavalue and may not increment";
            finish (-1);
        end if;
    end process;

等待100 ns;适应重置以确保计数器可以增加。可以提供不依赖于重置的c4b的设计描述。出于此目的，提供的c4b不会这样做。等待100 ns还提供count的采样间隔，其中c4b的组件声明是由clock事件驱动的自由运行。

将stim_process更改为未完成并等待：

-- -- Stimulus process
-- stim_process: process
-- begin
--     reset <= '0';                                   --because it only works when reset is 0!
--     wait for 100 ns;
--     if (count = "1111") then                        --the value is written to the text file in a continuous loop,
--         finish (0);                                     --which makes he file size go to as much as 1 GB
--     end if;                                             --thus to stop it at exactly one cycle!
-- end process;
-- END;

stim_process: 
    process
    begin
        reset <= '1';
        wait for 100 ns;
        reset <= '0';
        wait for 100 ns;
        wait;
    end process;

请注意，这也提供了在以下波形上看到的重置间隔。

这给了我们：

使用textio.txt的内容：

more fileio.txt

0000
  0001
  0010
  0011
  0100
  0101
  0110
  0111
  1000
  1001
  1010
  1011
  1100
  1101
  1110
  1111

在检测到count是＆＃34; 1111＆＃34;之后，也可以结束模拟。通过停止clock，避免使用完成程序。与使用Synopsys软件包std_logic_texio提供的写过程一起：

procedure WRITE(L:inout LINE; VALUE:in STD_LOGIC_VECTOR;

这将允许使用符合VHDL标准版本的VHDL仿真器，这些版本早于2008年。

无法将testbench的输出写入文件

1 个答案: