VHDL

时间:2016-05-02 06:59:06

标签: vhdl xilinx xilinx-ise

我想从文本文件中读取并在ISE环境中显示它,我有下面的代码,但是当我运行它时出现错误:

  

文件< ramfile_rd>不存在。

已创建,我在代码源所在的文件夹中有test.txt文件。

有什么问题?

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use std.textio.all ;
--use ieee.std_logic_textio.all;

use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_SIGNED.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

entity rd is

PORT(
 clk : IN   std_logic;
 a   : out  std_logic_vector (7 downto 0)

    );

end rd;

architecture Behavioral of rd is
--type Integerfiletype is file of integer ;

begin


read_from_file : process(clk)
   FILE ramfile_rd : text;
   variable RamFileLine_rd : line;
   variable di: integer;
     begin
       if(clk'event and clk='1') then

           file_open(ramfile_rd,"test.txt", read_mode);
            read (RamFileLine_rd,di);
            readline (ramfile_rd, RamFileLine_rd);
            a<=conv_std_logic_vector(di,8);
        file_close(ramfile_rd);

  end if;
 end process;
end Behavioral;

1 个答案:

答案 0 :(得分:0)

Heyyyy !!

尝试将代码编写为测试平台,它将进行模拟。 并在test.txt文件中插入一些整数值。模拟u将获得与测试文件中保存的值相同的值。

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use std.textio.all;
--use ieee.std_logic_textio.all;

use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_SIGNED.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

entity rd is
--PORT(
----     clk : IN   std_logic;
--     a   : out  std_logic_vector (7 downto 0)
--    );
end rd;

architecture Behavioral of rd is
signal  a : std_logic_vector(7 downto 0):="00000000";

begin

read_from_file : process
FILE ramfile_rd  : text;
variable line_num : line;
variable di       : integer:= 0;

 begin

--  if(clk'event and clk='1') then
     file_open(ramfile_rd ,"D:\test.txt", read_mode);
          while not endfile(ramfile_rd) loop 

          readline (ramfile_rd , line_num);
              read (line_num,di);
          a<=conv_std_logic_vector(di,8);
              wait for 10 ns; 
         end loop;
    file_close(ramfile_rd );

--  end if;
 end process;
 end Behavioral;