Question

我在VHDL代码中编写了2个状态机。模拟工作正常，但代码没有合成。任何帮助，将不胜感激。这是我的代码：

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_arith.ALL;
use IEEE.STD_LOGIC_unsigned.ALL;
use IEEE.NUMERIC_STD.ALL;

entity pulse_width is
Port (  clk : in STD_LOGIC;
            timer2:in std_logic;
            input: in STD_LOGIC;
            result: inout STD_LOGIC_VECTOR (15 downto 0);
            SEL_LINE: IN STD_LOGIC_VECTOR(5 DOWNTO 0);
            data_out: out STD_LOGIC_VECTOR (23 downto 0):=x"000000");
end pulse_width;

architecture Behavioral of pulse_width is
    TYPE count_states is (s0,s0_dash,s1,s2,s3,s1_dash);
    SIGNAL current_state, next_state : count_states := s0 ;
    TYPE write_states is (ws0,ws0_dash,ws1,ws2,ws3,ws4);
    SIGNAL current_state1, next_state1 : write_states := ws0 ;
    TYPE index_array is ARRAY(integer range 0 to 65535) of std_logic_vector(15 downto 0);
    SIGNAL mem: index_array;
    SIGNAL count: std_logic_vector(15 downto 0):=x"0000";
    SHARED VARIABLE j: integer:=0;
    SHARED VARIABLE a,i: integer:=1;
    SIGNAL flag,push_data,push_first,push_final,push_pulses,rw_first,rw_end: std_logic:='0';
    SIGNAL y_clk_input ,y_clk_timer2, enable_count: std_logic:='0';
    SIGNAL first,final: std_logic_vector(15 downto 0):= x"0001";

begin
-- Pulse width count

process (clk)
begin
    if rising_edge(clk) then
        current_state<=next_state;
        current_state1<=next_state1;
    end if;
end process;


process(input,SEL_LINE,current_state)
begin

------------------------------------------------------------------------
    case current_state is
    when s0 => 
        if(input='1') then
            next_state<=s1;
        else
            next_state<=s0;
        end if;
    when s1 =>
        flag<='0';
        if input='1' then
            count <= count+ x"0001";
            next_state<=s1_dash;
        else
            next_state<=s2;
        end if;         
    when s1_dash =>
        if input='1' then
            count <= count+ x"0001";
            next_state<=s1;
        else
            next_state<=s2;
        end if;         
    when s2 =>
            result <= count;
            next_state<=s3;
    when s3=>
            count <= x"0000";
            next_state<=s0;
            enable_count<='0';
    when others =>
        next_state<=s0;
    end case;

--------------------------------------------------------------------------
    case current_state1 is
    when ws0 =>
        if  (result>x"0000") then
        next_state1<=ws1;
        else
        next_state1<=ws0_dash;
        end if;
    when ws0_dash =>
        if  (result>x"0000") then
        next_state1<=ws1;
        else
        next_state1<=ws0;
        end if;
    when ws1=>
        if rw_first='1' and rw_end='1' then
        next_state1<=ws0;
        else
            mem(a) <= result;
            a:=a+1;
            final<=final+x"0001";
            next_state1<=ws2;
        end if;
    when ws2 =>
            next_state1<=ws0;
            result<=x"0000";
    when others  =>
        next_state1<=ws0;
    end case;
end process;

我最终需要实现三台状态机。

Answer 1

您在异步状态逻辑中尝试进行的数学运算未注册，也无法很好地合成。你需要重新安排你的状态逻辑，如：

count <= count+ x"0001";
...
final<=final+x"0001";

...是同步的，而不是“自由运行”。在异步循环中。

Answer 2

问题是你在一个组合过程中读写相同的信号。

将所有内容都置于一个时钟（同步）过程中
或：使用显式寄存器：count_next <= count + x"0001";

与您的错误无关，但仍值得关注：

你有大量未使用的信号和共享变量： push_data，push_first，push_final，push_pulses，y_clk_input，y_clk_timer2，first，i，j 对于试图阅读您的代码的任何人来说，这都令人困惑。 1

包STD_LOGIC_arith和STD_LOGIC_unsigned为deprecated

VHDL代码没有合成

2 个答案: