Question

在尝试实现D触发器并对其进行仿真时出现此错误：

VRFC 10-718]实体中不存在正式端口。请比较块的定义与其组件声明及其实例化以检测不匹配。

我是该语言的新手，不知道为什么会这样。

以下是我的VHDL代码。

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity Interfata is
port(
 clk : in std_logic;
 data :in std_logic;
 Q : out std_logic;
 Qnot : out std_logic
);

end Interfata;

architecture Behavioral of Interfata is

component LATCH 
  port(
   set : in std_logic;
   reset : in std_logic;
   data : out std_logic;
   data_not : out std_logic
  );
end component;

signal latch_set: std_logic;
signal latch_reset:std_logic;
begin
  uut1: latch port map(
    set => latch_set,
    reset => latch_reset,
    data => Q,
    data_not => Qnot
);

process(clk,data)
begin
  if(clk' event and clk='1') then
    latch_set <= data;
    latch_reset <= not data;
  end if;
end process;

end Behavioral;

这是latch.vhd代码

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;


entity latch is
port(
 set : in std_logic;
 reset :in std_logic;
 data : out std_logic;
 data_not : out std_logic

);
end latch;

architecture Behavioral of latch is
signal data_temp : std_logic:='0';
signal data_not_temp : std_logic:='1';
begin
  process(set, reset) begin
    data_temp <= not(reset or data_not_temp);
    data_not_temp <= not(set or data_temp);
    data <= data_temp;
    data_not <= data_not_temp;
  end process;
end Behavioral;

实体中不存在正式端口

0 个答案: