Question

我有这个简单的VHDL代码aufg4.vhd：

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity aufg4 is
    Port ( 
        clock : in  std_logic
            );
end aufg4;

architecture Behavioral of aufg4 is

    signal tut_counter : integer range 0 to 90 := 0; -- counts tutorial time

begin

    do_process :process(clock)
        begin
            if(rising_edge(clock)) then
                report "tut_counter " & integer'image(tut_counter);
                if(tut_counter >= 90) then
                    tut_counter <= 0;   
                    report "tut_counter reset";
                end if;
                tut_counter <= tut_counter + 1;
            end if;
        end process;

end Behavioral;

测试平台aufg4_tb.vhd：

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

ENTITY aufg4_tb IS
END aufg4_tb;

ARCHITECTURE behavior OF aufg4_tb IS 

     COMPONENT aufg4
     PORT(
        clock : IN  std_logic
          );
     END COMPONENT;

    --Inputs
    signal clock : std_logic := '0';

    -- Clock period definitions
    constant clock_period : time := 10 ns;

BEGIN

    -- Instantiate the Unit Under Test (UUT)
    uut: aufg4 PORT MAP (
    clock => clock
          );

    -- Clock process definitions
    clock_process :process
    begin
        clock <= '0';
        wait for clock_period/2;
        clock <= '1';
        wait for clock_period/2;
    end process;

END;

当我模拟行为模型report输出时：

 ...
at 885 ns(1): Note: tut_counter 88 (/aufg4_tb/uut/).
at 895 ns(1): Note: tut_counter 89 (/aufg4_tb/uut/).
at 905 ns(1): Note: tut_counter 90 (/aufg4_tb/uut/).
at 905 ns(1): Note: tut_counter reset (/aufg4_tb/uut/).
at 915 ns(1): Note: tut_counter 91 (/aufg4_tb/uut/).
at 915 ns(1): Note: tut_counter reset (/aufg4_tb/uut/).
at 925 ns(1): Note: tut_counter 92 (/aufg4_tb/uut/).
at 925 ns(1): Note: tut_counter reset (/aufg4_tb/uut/).
at 935 ns(1): Note: tut_counter 93 (/aufg4_tb/uut/).
...

因此if - 语句正常工作，但信号tut_counter的重新分配不起作用。

那为什么呢？

为什么模拟没有出错，因为tut_counter的范围是0 to 90？

Answer 1

使用path可以很好地解决问题！

else

否则您可以使用变量：do_process :process(clock) begin if(rising_edge(clock)) then report "tut_counter " & integer'image(tut_counter); if(tut_counter >= 90) then tut_counter := 0; report "tut_counter reset"; else tut_counter := tut_counter + 1; end if; end if; end process;

根据`report`语句

1 个答案: