Question

当我使用Xilinx 9.1i编译时，它告诉我：

＆＃34;第91行.Tens的类型与tensOut的类型不兼容。＆＃34;
＆＃34;第92行.Ones的类型与onesOut的类型不兼容。＆＃34;

但两者都是std_logic_vector（7 downto 0）

以下是代码：

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity BNG is
    Port ( Clk : in  STD_LOGIC;
           E : in  STD_LOGIC;
           BNRand : in  STD_LOGIC_VECTOR (6 downto 0);
           Letter : out  STD_LOGIC_VECTOR (7 downto 0);
           Tens : out  STD_LOGIC_VECTOR (7 downto 0);
           Ones : out  STD_LOGIC_VECTOR (7 downto 0));
end BNG;

architecture Behavioral of BNG is
    type states is (neutral, gen);
    signal current_state, next_state : states;
begin

    state_register: process(Clk)
    begin
        if rising_edge(Clk) then
            current_state <= next_state;
        end if;
    end process;

    next_logic: process(current_state)
    begin
        case current_state is
            when neutral => if E = '1' then next_state <= gen; else next_state <= neutral; end if;
            when gen => next_state <= neutral;
        end case;
    end process next_logic;

    logic: process(current_state)
        variable letterOut, tensOut, onesOut : std_logic_vector (7 downto 0);
        variable tens, ones : integer range 0 to 9;
        variable input : integer;
        constant B : std_logic_vector (7 downto 0) := "01000010";
        constant I : std_logic_vector (7 downto 0) := "01001001";
        constant N : std_logic_vector (7 downto 0) := "01001110";
        constant G : std_logic_vector (7 downto 0) := "01000111";
        constant O : std_logic_vector (7 downto 0) := "01001111";
        constant zero : std_logic_vector (7 downto 0) := "00110000";
    begin
        if current_state = gen then
            input := conv_integer( unsigned(BNRand) );
            tens := input / 10;
            ones := input mod 10;

            if (input > 0) and (input < 16) then
                letterOut := B;
            elsif (input > 15) and (input < 31) then
                letterOut := I;
            elsif (input > 30) and (input < 46) then
                letterOut := N;
            elsif (input > 45) and (input < 61) then
                letterOut := G;
            elsif (input > 60) and (input < 76) then
                letterOut := O;
            end if;

            tensOut := zero + std_logic_vector( conv_unsigned(tens, 8) );
            onesOut := zero + std_logic_vector( conv_unsigned(ones, 8) );
        end if;
        Letter <= letterOut;
        Tens <= tensOut;
        Ones <= onesOut;
    end process logic;

end Behavioral;

Answer 1

在VHDL中，标识符不区分大小写。标识符Tens和Ones被声明为端口，而标识符tens和ones在过程中被声明为变量。因此，流程中Tens <= tensOut;和Ones <= onesOut;的分配可以看到变量tens和ones，而不是端口。

一种有用的编码风格是命名带有结尾_v的变量，从而获得tens_v和ones_v，这也有助于记住<=的分配类型信号和:=变量。

这个信号分配有什么问题？

1 个答案: