Question

我正在尝试使用Quartus II 13.1编写BCD加法器的示例代码。

LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;

ENTITY bcdadder IS
    PORT(
        c0      : IN STD_LOGIC;
        a,b : IN STD_LOGIC_VECTOR(4 downto 1);
        c4      : OUT STD_LOGIC;
        sum : OUT STD_LOGIC_VECTOR(4 downto 1));
END bcdadder;

ARCHITECTURE    adder OF bcdadder IS
-- component declaration
COMPONENT add4par IS
PORT(
    c0  : IN STD_LOGIC;
    a,b: IN STD_LOGIC_VECTOR(4 downto 1);
    c4 : OUT STD_LOGIC;
    sum: OUT STD_LOGIC_VECTOR(4 downto 1));
END COMPONENT;

SIGNAL c4_bin   : STD_LOGIC;
SIGNAL c4_bcd   : STD_LOGIC;
SIGNAL sum_bin  : std_LOGIC_VECTOR(4 downto 1);
SIGNAL binary   : std_LOGIC_VECTOR(5 downto 1);
SIGNAL a_bcd    : std_LOGIC_VECTOR(4 downto 1);
SIGNAL c0_bcd   : std_LOGIC;

BEGIN
--Instantinate 4-bit adder (binary sum)
    add_bin: add4par
        PORT MAP ( c0 => c0_bcd,
                      a  => a,
                      b  => b,
                      c4 => c4_bin,
                      sum => sum_bin);

--Instantinate 4-bit adder (binary-BCD converter)
    converter: add4par
        PORT MAP (c0  => c0_bcd,
                     a   => a_bcd,
                     b    => sum_bin,
                     sum => sum);

--BCD carry input (code converter has no input carry)
    c0_bcd <= '0';

--Concancenate binary carry and sum for comparison functions
    binary <= c4_bin & sum_bin;
--Generate a BCD carry for number from 10 to 19
    --If there is a BCD carry, add 6 to sum
    --If no BCD carry, add 0
PROCESS(binary)
BEGIN   
    --This comparison requires std_logic_unsigned package
    IF (binary >= "01010" and binary <= "10011") THEN
        c4_bcd <= '1';
        a_bcd  <= "0110";
    ELSE
        c4_bcd <= '0';
        a_bcd  <= "0000";
    END IF;
END PROCESS;

--Map c4 port to internal BCD carry
c4 <= c4_bcd;

END adder;

这是我得到的错误

错误（12006）：节点实例“add_bin”实例化未定义的实体“add4par”

错误（12006）：节点实例“converter”实例化未定义的实体“add4par”

错误：Quartus II 64位分析＆amp;合成不成功。 2个错误，0个警告

我曾经通过创建一个单独的实体而不是组件来解决这个问题而且它有效，但现在我需要使用组件。 Altera建议的解决方案都没有帮助。

请提出任何建议。

Quartus错误（12006）节点实例实例化未定义的实体

0 个答案: