当我尝试使用Quartus将代码编译到我的DE2板上时出现一些奇怪的错误。我的朋友在他的计算机上尝试了我的代码并且编译没有错误，但是在我的计算机上，它给了我以下错误。
Info: Running Quartus II 64-Bit Analysis & Synthesis
Info: Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
Info: Processing started: Sun May 17 15:11:37 2015
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off 353lab2 -c lab2
Warning (20028): Parallel compilation is not licensed and has been disabled
Error (10430): VHDL Primary Unit Declaration error at std_logic_1164.vhd(51): primary unit "std_logic_1164" already exists in library "ieee"
Error (10784): HDL error at std_1164.vhd(46): see declaration for object "std_logic_1164"
Error (10430): VHDL Primary Unit Declaration error at syn_unsi.vhd(34): primary unit "STD_LOGIC_UNSIGNED" already exists in library "ieee"
Error (10784): HDL error at std_logic_unsigned.vhd(30): see declaration for object "STD_LOGIC_UNSIGNED"
Error (10431): VHDL Secondary Unit Declaration error at std_logic_1164.vhd(252): secondary unit "std_logic_1164" already exists in primary unit "std_logic_1164"
Error (10784): HDL error at std_1164.vhd(246): see declaration for object "std_logic_1164"
Error (10523): Ignored construct STD_LOGIC_UNSIGNED at std_logic_unsigned.vhd(87) due to previous errors
Error (10523): Ignored construct VITAL_Timing at timing_b.vhd(54) due to previous errors
Error (10523): Ignored construct LPM_COMPONENTS at lpm_pack.vhd(678) due to previous errors
Error (10523): Ignored construct std_logic_arith at mgc_arit.vhd(270) due to previous errors
Error (10523): Ignored construct qsim_logic at mgc_qsim.vhd(755) due to previous errors
Error (10523): Ignored construct TEXTIO at textio_vhdl93.vhd(103) due to previous errors
Error (10523): Ignored construct std_logic_arith at syn_arit.vhd(204) due to previous errors
Error (10523): Ignored construct std_logic_misc at syn_misc.vhd(182) due to previous errors
Error (10523): Ignored construct STD_LOGIC_SIGNED at syn_sign.vhd(95) due to previous errors
Error (10523): Ignored construct std_logic_textio at syn_textio.vhd(68) due to previous errors
Error (10523): Ignored construct STD_LOGIC_UNSIGNED at syn_unsi.vhd(93) due to previous errors
Info (12021): Found 2 design units, including 1 entities, in source file lab2.vhd
Info (12022): Found design unit 1: lab2-impl
Info (12023): Found entity 1: lab2
Info (12021): Found 2 design units, including 1 entities, in source file dflip.vhd
Info (12022): Found design unit 1: dFlip-impl
Info (12023): Found entity 1: dFlip
Error: Quartus II 64-Bit Analysis & Synthesis was unsuccessful. 17 errors, 1 warning
Error: Peak virtual memory: 529 megabytes
Error: Processing ended: Sun May 17 15:11:38 2015
Error: Elapsed time: 00:00:01
Error: Total CPU time (on all processors): 00:00:01
根据我的理解，Quartus可能会在＆＃34; ieee＆＃34;中检测到std_logic_1164的多个副本，但是当我点击错误时，它会将我带到quartus / libraries / ieee / std_logic_1164.vhd。