Question

我在尝试编译以下代码时遇到问题：

----------------
----------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity adder_top is
Port ( a_in : in STD_LOGIC_VECTOR (3 downto 0);
       b_in : in STD_LOGIC_VECTOR (3 downto 0);
       clk : in STD_LOGIC;
       clk_en : in STD_LOGIC;
       carry_in : in STD_LOGIC;
       carry_out : out STD_LOGIC;
       c_out : out STD_LOGIC_VECTOR (3 downto 0));
end adder_top;

architecture Behavioral of adder_top is
COMPONENT c_addsub_0
  PORT (
    A : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
    B : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
    CLK : IN STD_LOGIC;
    C_IN : IN STD_LOGIC;
    CE : IN STD_LOGIC;
    C_OUT : OUT STD_LOGIC;
    S : OUT STD_LOGIC_VECTOR(3 DOWNTO 0)
  );
END COMPONENT c_addsub_0;
begin
inst_1 : COMPONENT c_addsub_0
    port map
    (
        A => a_in,
        B => b_in,
        CLK => clk,
        C_IN => carry_in,
        CE => clk_en,
        C_OUT => carry_out,
        S => c_out
    );

end Behavioral;

---------------------------
---------------------------

尝试编译时收到以下错误代码：

错误（12006）：节点实例“inst_1”实例化未定义的实体 “c_addsub_0”。确保指定了所需的库路径正确地，定义指定的实体，或更改实例化。如果此实体代表Intel FPGA或第三方IP，则生成 IP的综合文件。

我完全不确定为什么我收到此错误。任何帮助将不胜感激。

Quartus Prime VHDL组件实例化编译错误

0 个答案: