Question

我正在使用Altera Max V和Quartus学习VHDL来做一些例子，我在使用＆＃34时遇到了麻烦;使用选择＆＃34;声明。我有一个简单的2-4解码器如下：

library ieee;
use ieee.std_logic_1164.all;

entity lesson9 is
    port(
        x: in std_logic_vector(1 downto 0);
        en: in std_logic;
        y: out std_logic_vector(3 downto 0)
    );
end lesson9;

architecture rtl of lesson9 is

signal outputBuff: std_logic_vector(3 downto 0);

begin
    decoder2to4: process(x)
    begin
        with x select
            outputBuff <= "0001" when "00",
                          "0010" when "01",
                          "0100" when "10",
                          "1000" when "11";
    end process decoder2to4;

    y <= outputBuff;
end rtl;

我收到了错误消息：

近文字＆＃34;与＆＃34 ;;期待＆＃34;结束＆＃34;，或＆＃34;（＆＃34;或标识符（＆＃34;＆＃34;是保留关键字），pr a sequential statement

我试图查看我的代码，但无法找到问题？

Answer 1

with ... select语句是在进程外使用的并发信号赋值语句：

architecture rtl of lesson9 is

signal outputBuff: std_logic_vector(3 downto 0);

begin
    with x select
        outputBuff <= "0001" when "00",
                      "0010" when "01",
                      "0100" when "10",
                      "1000" when "11";

    y <= outputBuff when en='1' else (others=>'0');
end rtl;

我还在输出赋值语句中添加了en信号。

注意：我没有模拟该代码段。

VHDL：使用＆＃34时出错;选择何时＆＃34;声明

1 个答案: