WITH - 具有多个条件的SELECT语句（VHDL）

Question

在VHDL中选择语句，在多个案例中分配相同的信号：
with ALUop select z <= s_add_sub when "00000", s_add_sub when "00001", s_add_sub when "00010", s_add_sub when "00011", x AND y when "00100", x OR y when "00101", x XOR y when "00110", lhi when "00111", seq when "01000", sne when "01001", slt when "01010", sgt when "01011", sle when "01100", sge when "01101", NOT x when "01110", x when "01111", shift_out when "10000", shift_out when "10001", shift_out when "10010", y when "10011", x"00000000" when others;
如何更改语句，以便在多个条件下仅在一行中进行赋值，如：

with ALUop select z <= s_add_sub when "00000" OR "00001" OR "00010" OR "00011",...

Answer 1

使用|而非OR进行多项选择，从而制作如下代码：

with ALUop select 
  z <= s_add_sub when "00000" | "00001" | "00010" | "00011", 
       x AND y when "00100", 
       ...

这类似于case的多个选择的语法。