使用我的VHDL代码提供帮助 尝试使用IF语句选择输入到输出的输入 使用WITH XXX选择
是选择 d和e 是4输入 y是输出
帮助 感谢
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.all;
ENTITY mux_4_1 IS
PORT(
S : in STD_LOGIC;
d : IN STD_LOGIC_VECTOR (3 downto 0);
e : IN STD_LOGIC_VECTOR (3 downto 0);
y : OUT STD_LOGIC_VECTOR (0 to 6));
END mux_4_1;
ARCHITECTURE behavior OF mux_4_1 is
BEGIN
PROCESS(S,d,e)
BEGIN
IF S = '0' THEN
WITH d SELECT
y <= "1111110" WHEN "0000",--0
"0110000" WHEN "0001",--1
"1101101" WHEN "0010",--2
"1111001" WHEN "0011",--3
"0110011" WHEN "0100",--4
"1011011" WHEN "0101",--5
"1011111" WHEN "0110",--6
"1110000" WHEN "0111",--7
"1111111" WHEN "1000",--8
"1111011" WHEN "1001",--9
"0000000" when others;
ELSE S = '1' THEN
WITH e SELECT
y <= "1111110" WHEN "0000",--0
"0110000" WHEN "0001",--1
"1101101" WHEN "0010",--2
"1111001" WHEN "0011",--3
"0110011" WHEN "0100",--4
"1011011" WHEN "0101",--5
"1011111" WHEN "0110",--6
"1110000" WHEN "0111",--7
"1111111" WHEN "1000",--8
"1111011" WHEN "1001",--9
"0000000" when others;
END IF;
END PROCESS;
END behavior;
错误(10500):mux_4_1.vhd(23)处文本“WITH”附近的VHDL语法错误;期望“结束”,或“(”或标识符(“with”是保留关键字)或顺序语句
错误(10500):mux_4_1.vhd(25)处文本“WHEN”附近的VHDL语法错误;期待“;”
答案 0 :(得分:-1)
我从你所给出的内容中唯一的错误就是在then
陈述之后没有else
。