用于分割大小为1000的源信号的Verilog代码

Question

我是Verilog的初学者，所以请帮我解决以下代码 我想实现：

module division (input clk, 
                 input rst, 
                 input [15:0]din, 
                 output [15:0]out);

  reg signed [15:0] a;//this will have max value among din value 
  reg signed [15:0] b;//this will have min value among din value 
  reg signed [15:0] z;//

 always @ (posedge clk)
  if (rst)
    z <= 0;
  else
    z <= (din-min) / (max-min); // in which din is source signal having size of 1000

assign out=z;

endmodule

上面代码中的问题是din是可变的，当我在Xilinx中合成此代码时，它会给我一个不支持Div运算符的错误。

应该如何实现？提前谢谢..