单位<modem_ctrl_logic>上的多源信号<mcr <4>&gt;

时间:2016-07-14 01:22:35

标签: verilog system-verilog

module Modem_Ctrl_Logic
(
 input cts_b,dsr_b,dcd_b,ri_b,clk,
 output reg rts_b,dtr_b,out1_b,out2_b,
 input [4:0] mcr,
 output reg [7:0]msr
);

reg x;

always @(posedge clk)
begin
    msr[0] = cts_b;
    msr[1] = dsr_b;
    msr[2] = dcd_b;
    msr[3] = ri_b ;

    rts_b = mcr[0];
    dtr_b = mcr[1];
    out1_b = mcr[2];
    out2_b = mcr[3];
    x      = mcr[4];

    if (x == 1)

            rts_b = cts_b;
            dtr_b = dsr_b;
            out1_b= dcd_b;
            out2_b =    ri_b;


end

Modem_Control_Reg m1 (.MCo(mcr));

endmodule

我收到此错误

  

xst: - 单位信号上的528多源&gt ;;

0 个答案:

没有答案