Question

嘿伙计们我正在尝试用VHDL实现32x6RAM而且我发誓一切看起来都很好，在我浏览了我的源代码之后但我似乎无法弄清楚为什么当我尝试时我得到一个悬空信号/多源错误创建S =＆gt; AD（0）到S =＆gt; AD（31）...任何人都可以帮我指出我的代码中可能会遗忘的内容吗？

Code:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

--Uncomment the following library declaration if instantiating
--any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity mm32by6RAM is
    Port ( OE   : in    STD_LOGIC;
           CS   : in    STD_LOGIC;
           RW   : in    STD_LOGIC;
           A    : in    STD_LOGIC_VECTOR (4 downto 0);
           D    : out   STD_LOGIC_VECTOR (5 downto 0));
end mm32by6RAM;

architecture Behavioral of mm32by6RAM is

COMPONENT mm5to32Decoder
    Port ( A    : in    STD_LOGIC_VECTOR (4 downto 0);
           OEB : in     STD_LOGIC;
           Z    : out   STD_LOGIC_VECTOR (31 downto 0));
end COMPONENT;


COMPONENT mm1by6RAM
    Port ( I : in   STD_LOGIC_VECTOR (5 downto 0);
           W : in   STD_LOGIC;
           R : in   STD_LOGIC;
           S : in   STD_LOGIC;
              D : out   STD_LOGIC_VECTOR (5 downto 0));
end COMPONENT;


COMPONENT mmOutputBuffer
    Port ( B    : in    STD_LOGIC_VECTOR(5 downto 0);
           OE   : in    STD_LOGIC;
           D    : out   STD_LOGIC_VECTOR (5 downto 0));
end COMPONENT;


COMPONENT mm3NOR 
    Port ( A : in   STD_LOGIC;
           B : in   STD_LOGIC;
           C : in   STD_LOGIC;
           Z : out      STD_LOGIC);
end COMPONENT;


COMPONENT mmINVERT
    Port ( a : in       STD_LOGIC;
           z : out      STD_LOGIC);
end COMPONENT;


SIGNAL RWnot        :   STD_LOGIC;
SIGNAL N                :   STD_LOGIC;
SIGNAL OB           :   STD_LOGIC_VECTOR (5 downto 0);
SIGNAL AD           :   STD_LOGIC_VECTOR (31 downto 0);
SIGNAL Ram          :   STD_LOGIC_VECTOR (5 downto 0);

begin

gate1       :   mmINVERT            PORT MAP    (a=>RW,     z=>RWnot);
gate2       :   mm3NOR          PORT MAP    (A=>OE,     B=>CS,      C=>RWnot,   Z=>N);
gate3       :   mmOutputBuffer  PORT MAP    (B=>Ram, OE=>N,         D=>OB);
gate4       :   mm5to32Decoder  PORT MAP    (A=>A,  OEB=>CS,        Z=>AD);

gate5       :   mm1by6RAM       PORT MAP    (I=>OB,     W=>RWnot,   R=>RW,  S=>AD(0),   D=>Ram);
gate6       :   mm1by6RAM       PORT MAP    (I=>OB, W=>RWnot,   R=>RW,  S=>AD(1),   D=>Ram);
--gate7     :   mm1by6RAM       PORT MAP    (I=>OB, W=>RWnot,   R=>RW,  S=>AD(2),   D=>Ram);
--gate8     :   mm1by6RAM       PORT MAP    (I=>OB, W=>RWnot,   R=>RW,  S=>AD(3),   D=>Ram);
--gate9     :   mm1by6RAM       PORT MAP    (I=>OB, W=>RWnot,   R=>RW,  S=>AD(4),   D=>Ram);
--gate10    :   mm1by6RAM       PORT MAP    (I=>OB, W=>RWnot,   R=>RW,  S=>AD(5),   D=>Ram);
--gate11    :   mm1by6RAM       PORT MAP    (I=>OB, W=>RWnot,   R=>RW,  S=>AD(6),   D=>Ram);
--gate12    :   mm1by6RAM       PORT MAP    (I=>OB, W=>RWnot,   R=>RW,  S=>AD(7),   D=>Ram);
--gate13    :   mm1by6RAM       PORT MAP    (I=>OB, W=>RWnot,   R=>RW,  S=>AD(8),   D=>Ram);
--gate14    :   mm1by6RAM       PORT MAP    (I=>OB, W=>RWnot,   R=>RW,  S=>AD(9),   D=>Ram);
--gate15    :   mm1by6RAM       PORT MAP    (I=>OB, W=>RWnot,   R=>RW,  S=>AD(10),  D=>Ram);
--gate16    :   mm1by6RAM       PORT MAP    (I=>OB, W=>RWnot,   R=>RW,  S=>AD(11),  D=>Ram);
--gate17    :   mm1by6RAM       PORT MAP    (I=>OB, W=>RWnot,   R=>RW,  S=>AD(12),  D=>Ram);
--gate18    :   mm1by6RAM       PORT MAP    (I=>OB, W=>RWnot,   R=>RW,  S=>AD(13),  D=>Ram);
--gate19    :   mm1by6RAM       PORT MAP    (I=>OB, W=>RWnot,   R=>RW,  S=>AD(14),  D=>Ram);
--gate20    :   mm1by6RAM       PORT MAP    (I=>OB, W=>RWnot,   R=>RW,  S=>AD(15),  D=>Ram);
--gate21    :   mm1by6RAM       PORT MAP    (I=>OB, W=>RWnot,   R=>RW,  S=>AD(16),  D=>Ram);
--gate22    :   mm1by6RAM       PORT MAP    (I=>OB, W=>RWnot,   R=>RW,  S=>AD(17),  D=>Ram);
--gate23    :   mm1by6RAM       PORT MAP    (I=>OB, W=>RWnot,   R=>RW,  S=>AD(18),  D=>Ram);
--gate24    :   mm1by6RAM       PORT MAP    (I=>OB, W=>RWnot,   R=>RW,  S=>AD(19),  D=>Ram);
--gate25    :   mm1by6RAM       PORT MAP    (I=>OB, W=>RWnot,   R=>RW,  S=>AD(20),  D=>Ram);
--gate26    :   mm1by6RAM       PORT MAP    (I=>OB, W=>RWnot,   R=>RW,  S=>AD(21),  D=>Ram);
--gate27    :   mm1by6RAM       PORT MAP    (I=>OB, W=>RWnot,   R=>RW,  S=>AD(22),  D=>Ram);
--gate28    :   mm1by6RAM       PORT MAP    (I=>OB, W=>RWnot,   R=>RW,  S=>AD(23),  D=>Ram);
--gate29    :   mm1by6RAM       PORT MAP    (I=>OB, W=>RWnot,   R=>RW,  S=>AD(24),  D=>Ram);
--gate30    :   mm1by6RAM       PORT MAP    (I=>OB, W=>RWnot,   R=>RW,  S=>AD(25),  D=>Ram);
--gate31    :   mm1by6RAM       PORT MAP    (I=>OB, W=>RWnot,   R=>RW,  S=>AD(26),  D=>Ram);
--gate32    :   mm1by6RAM       PORT MAP    (I=>OB, W=>RWnot,   R=>RW,  S=>AD(27),  D=>Ram);
--gate33    :   mm1by6RAM       PORT MAP    (I=>OB, W=>RWnot,   R=>RW,  S=>AD(28),  D=>Ram);
--gate34    :   mm1by6RAM       PORT MAP    (I=>OB, W=>RWnot,   R=>RW,  S=>AD(29),  D=>Ram);
--gate35    :   mm1by6RAM       PORT MAP    (I=>OB, W=>RWnot,   R=>RW,  S=>AD(30),  D=>Ram);
--gate36    :   mm1by6RAM       PORT MAP    (I=>OB, W=>RWnot,   R=>RW,  S=>AD(31),  D=>Ram);



end Behavioral;

以下是它应遵守的设计原理图：

http://www.cse.psu.edu/~kyusun/class/cmpen471/12f/hw/pj4/ram32x6.gif

谢谢你们！

Answer 1

您的每个mm1by6RAM都需要输出一个唯一的信号。然后使用选择信号AD，您可以选择哪一个是正确的信号。

该工具不知道为你做那件事。

您需要以下内容：

Ram <= Output_from_gate0 when AD(0) = '1' else
       Output_from_gate1 when AD(1) = '1' else
       Output_from_gate2 when AD(2) = '1' else
       ...

VHDL多源/悬空信号错误xst：528

1 个答案: