我有一个项目，我使用内存（24x12），当okk内部信号取值为4时写入内存，当我生成编程文件时，我的内存中的每一位都会出现xst 737错误。
有人可以帮我解决这些问题吗？
主体系结构的部分代码：
library IEEE;
use IEEE.STD_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity Termostat is
port (set: in std_logic; -- intrare folosita
pentru intrarea in modul de setare
s: in std_logic_vector(1 downto 0); -- intrare pentru a alege
modul de setare -> 3 stari de setare
clk: in std_logic; -- intrare de clock de pe
placa
plus, minus: in std_logic; -- butoane pentru setarea
manuala a componentelor
ok: in std_logic;
mode: out std_logic; -- iesire care indica daca
incalzirea este pornita sau nu
anod:out std_logic_vector(7 downto 0); -- iesire pentru afisorul 7-segmente
display:out std_logic_vector(6 downto 0)); -- iesire pentru afisorul 7-segmente cu cifra de afisat
end Termostat;
architecture TERM of Termostat is
component Ceas is
port (clk, set, plus, ok, minus: in std_logic;
ora: out std_logic_vector (4 downto 0);
min: out std_logic_vector (5 downto 0));
end component Ceas;
component debounce is
port (buton:in std_logic;
clk: in std_logic;
buton_out: out std_logic);
end component debounce;
component US is
port (temp, t_min, t_max:in std_logic_vector(5 downto 0);
clk, set:in std_logic;
puls, mode:out std_logic);
end component US;
component Termistor is
port (set, minus, plus, clk:in std_logic;
temp_mod, puls:in std_logic;
temp:out std_logic_vector(5 downto 0));
end component Termistor;
component UMDT is
port (ora:in std_logic_vector(4 downto 0); set, plus, minus, ok, clk:in std_logic;
temp_min, temp_max:out std_logic_vector(5 downto 0);
ora1, ora2:out std_logic_vector(4 downto 0);
t_min_set, t_max_set:out std_logic_vector(5 downto 0));
end component UMDT;
component bcd5 is
port (in_vect:in std_logic_vector(4 downto 0); out_vect:out std_logic_vector(7 downto 0));
end component bcd5;
component bcd6 is
port (in_vect:in std_logic_vector(5 downto 0); out_vect:out std_logic_vector(7 downto 0));
end component bcd6;
component afisor is
port (af:in std_logic_vector(31 downto 0); clk:in std_logic;
display:out std_logic_vector(6 downto 0); anod:out std_logic_vector(7 downto 0));
end component afisor;
signal ora: std_logic_vector(4 downto 0) := (others =>'0'); -- ora indicata de ceas
signal ora1, ora2: std_logic_vector(4 downto 0) := (others =>'0'); -- semanale utiliate la setarea intervalelor de temp. pe ore dela ora1 la ora2
signal min: std_logic_vector(5 downto 0) := (others =>'0'); -- min indicate de ceas
signal temp: std_logic_vector(5 downto 0) := (others =>'0'); -- temp indicata de termistor
signal t_min, t_max: std_logic_vector(5 downto 0) := (others =>'0');-- temp minima si maxima corescunzatoare pt ora actuala de la UMDT la US
signal t_max_set, t_min_set: std_logic_vector(5 downto 0) := (others =>'0');-- temp minima si maxima utilizate la setarea intervalelor de temp pe ore
signal plus_deb, ok_deb, minus_deb: std_logic :='0'; -- iesirile de la debouncerele pentru butoane
signal t_mode: std_logic :='0'; -- modul de functionare al incalziri transmis de la US la termistor
signal puls: std_logic :='0'; -- semnal de clock trasmis de la US la termistor cu perioada 3 sec
signal com0, com1, com2, com3: std_logic :='0'; -- semnalele de comanda
signal af_sig: std_logic_vector (31 downto 0):= (others =>'0'); -- semnalul de afisat transmis la afisor
signal ora_bcd, ora1_bcd, ora2_bcd, temp_bcd, min_bcd, t_min_bcd, t_max_bcd: std_logic_vector (7 downto 0) := (others =>'0');
-- iesirile transformate in bcd ale valorilor de afisat
begin
com0<='1' when (set='0' or (s(1)='0' and s(0)='0')) else '0';
com1<='1' when (set='1' and s(0)='1' and s(1)='0') else '0';
com2<='1' when (set='1' and s(0)='0' and s(1)='1') else '0';
com3<='1' when (set='1' and s(0)='1' and s(1)='1') else '0';
deb1: debounce port map (buton =>plus, clk =>clk, buton_out =>plus_deb);
deb2: debounce port map (buton =>minus, clk =>clk, buton_out =>minus_deb);
deb3: debounce port map (buton =>ok, clk =>clk, buton_out =>ok_deb);
c1: Ceas port map (set =>com2, clk =>clk, min =>min, minus =>minus_deb, plus =>plus_deb, ok =>ok_deb, ora =>ora);
c2: US port map (temp =>temp, t_min =>t_min, t_max =>t_max, clk =>clk, puls =>puls, mode =>t_mode, set =>com0);
c3: Termistor port map (set =>com1, plus =>plus_deb, minus =>minus_deb, clk =>clk, temp_mod =>t_mode, puls =>puls, temp =>temp);
c4: UMDT port map (set =>com3, plus =>plus_deb, ok =>ok_deb, minus =>minus_deb, clk =>clk, ora =>ora, temp_min =>t_min,
temp_max =>t_max, t_min_set =>t_min_set, t_max_set =>t_max_set, ora1 =>ora1, ora2 =>ora2);
end architecture;
以及提供错误的组件：
library IEEE;
use IEEE.STD_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity UMDT is
port (ora:in std_logic_vector(4 downto 0); -- ora actuala
set:in std_logic; -- intrare de set pt intervale de temp
plus, minus, ok:in std_logic; -- butoanele + ,- si ok
clk:in std_logic; -- clock de la placa
temp_min, temp_max:out std_logic_vector(5 downto 0); -- temp minima si temp maxima corestunzatoare pt ora actuala
ora1, ora2:out std_logic_vector(4 downto 0); -- orele din modul set de afisat
t_min_set, t_max_set:out std_logic_vector(5 downto 0)); -- temperaturile din modul set de afisat
end UMDT;
architecture struct of UMDT is
constant timer:integer :=20;--_000_000; -- 5 cresteri pe secunda in modul set
type lin is array(11 downto 0) of std_logic;
type memory is array(0 to 23) of lin;
signal mem: memory :=(others => "010100010001"); -- memoria utilizata pt retinerea intervalelor de temp, tmax si tmin initial 20 respectiv 17
signal o1, o2: std_logic_vector(4 downto 0) := (others => '0'); -- semanle utilizate pt setarea intervalelor orare
signal t_min, t_max, t1, t2: std_logic_vector(5 downto 0) := (others => '0'); -- semanle utilizate pt setarea intervalelor temperaturilor,
temperaturile de iesire t_min si t_max acutale
signal mem_line, mem_ora: lin := (others =>'0');
signal okk: std_logic_vector(2 downto 0):= "000"; -- semnal de selectie
signal oo1, oo2, oo:integer range 0 to 23 :=0; -- valoare intreaga a semnalelor o1, o2 si ora
signal guard: std_logic := '0'; -- utilizata pt scrierea in memorie
signal perioada: std_logic_vector (23 downto 0) := (others =>'0'); -- utilizat pt cresterea de 5 ori intr o secunda in modul set
begin
okay: process (ok)
begin
if ok='1' then
okk<=okk+1;
end if;
if okk=4 then
okk<="000";
end if;
end process okay;
sett: process (okk, set, plus, minus, clk, o1, o2, t_min, t_max)
begin
if clk='1' and clk'event then
if set='1' then
perioada<=perioada+1;
if plus='1' then
if perioada>=timer then
perioada<=(others =>'0');
case okk is
when "000" =>
o1<=o1+1;
if o1=23 then
o1<="00000";
end if;
when "001" =>
o2<=o2+1;
if o2=23 then
o2<="00000";
end if;
when "010" =>
t_min<=t_min+1;
when "011" =>
t_max<=t_max+1;
when others => null;
end case;
end if;
end if;
if minus='1' then
if perioada=timer then
perioada<=perioada+1;
case okk is
when "000" =>
o1<=o1-1;
if o1=23 then
o1<="10111";
end if;
when "001" =>
o2<=o2-1;
if o2=0 then
o2<="10111";
end if;
when "010" =>
t_min<=t_min-1;
when "011" =>
t_max<=t_max-1;
when others => null;
end case;
end if;
end if;
end if;
end if;
end process sett;
oo1<=conv_integer(o1);
oo2<=conv_integer(o2);
ora1<=o1;
ora2<=o2;
t_min_set<=t_min;
t_max_set<=t_max;
mem_line(11)<= t_max(5);
mem_line(10)<= t_max(4);
mem_line(9)<= t_max(3);
mem_line(8)<= t_max(2);
mem_line(7)<= t_max(1);
mem_line(6)<= t_max(0);
mem_line(5)<= t_min(5);
mem_line(4)<= t_min(4);
mem_line(3)<= t_min(3);
mem_line(2)<= t_min(2);
mem_line(1)<= t_min(1);
mem_line(0)<= t_min(0);
guard<= '1' when (okk=4) else '0';
mem(0)<=mem_line when (guard='1') and ((oo1=0) or ((oo1>oo2) and (0<oo2)) or (oo1=oo2)) else mem(0);
mem(1)<=mem_line when (guard='1') and (((oo1<=1) and (1<oo2)) or ((oo1>oo2) and (1<oo2)) or (oo1=oo2));
mem(2)<=mem_line when (guard='1') and (((oo1<=2) and (2<oo2)) or ((oo1>oo2) and (2<oo2)) or (oo1=oo2));
mem(3)<=mem_line when (guard='1') and (((oo1<=3) and (3<oo2)) or ((oo1>oo2) and (3<oo2)) or (oo1=oo2));
mem(4)<=mem_line when (guard='1') and (((oo1<=4) and (4<oo2)) or ((oo1>oo2) and (4<oo2)) or (oo1=oo2));
mem(5)<=mem_line when (guard='1') and (((oo1<=5) and (5<oo2)) or ((oo1>oo2) and (5<oo2)) or (oo1=oo2));
mem(6)<=mem_line when (guard='1') and (((oo1<=6) and (6<oo2)) or ((oo1>oo2) and (6<oo2)) or (oo1=oo2));
mem(7)<=mem_line when (guard='1') and (((oo1<=7) and (7<oo2)) or ((oo1>oo2) and (7<oo2)) or (oo1=oo2));
mem(8)<=mem_line when (guard='1') and (((oo1<=8) and (8<oo2)) or ((oo1>oo2) and (8<oo2)) or (oo1=oo2));
mem(9)<=mem_line when (guard='1') and (((oo1<=9) and (9<oo2)) or ((oo1>oo2) and (9<oo2)) or (oo1=oo2));
mem(10)<=mem_line when (guard='1') and (((oo1<=10) and (10<oo2)) or ((oo1>oo2) and (10<oo2)) or (oo1=oo2));
mem(11)<=mem_line when (guard='1') and (((oo1<=11) and (11<oo2)) or ((oo1>oo2) and (11<oo2)) or (oo1=oo2));
mem(12)<=mem_line when (guard='1') and (((oo1<=12) and (12<oo2)) or ((oo1>oo2) and (12<oo2)) or (oo1=oo2));
mem(13)<=mem_line when (guard='1') and (((oo1<=13) and (13<oo2)) or ((oo1>oo2) and (13<oo2)) or (oo1=oo2));
mem(14)<=mem_line when (guard='1') and (((oo1<=14) and (14<oo2)) or ((oo1>oo2) and (14<oo2)) or (oo1=oo2));
mem(15)<=mem_line when (guard='1') and (((oo1<=15) and (15<oo2)) or ((oo1>oo2) and (15<oo2)) or (oo1=oo2));
mem(16)<=mem_line when (guard='1') and (((oo1<=16) and (16<oo2)) or ((oo1>oo2) and (16<oo2)) or (oo1=oo2));
mem(17)<=mem_line when (guard='1') and (((oo1<=17) and (17<oo2)) or ((oo1>oo2) and (17<oo2)) or (oo1=oo2));
mem(18)<=mem_line when (guard='1') and (((oo1<=18) and (18<oo2)) or ((oo1>oo2) and (18<oo2)) or (oo1=oo2));
mem(19)<=mem_line when (guard='1') and (((oo1<=19) and (19<oo2)) or ((oo1>oo2) and (19<oo2)) or (oo1=oo2));
mem(20)<=mem_line when (guard='1') and (((oo1<=20) and (20<oo2)) or ((oo1>oo2) and (20<oo2)) or (oo1=oo2));
mem(21)<=mem_line when (guard='1') and (((oo1<=21) and (21<oo2)) or ((oo1>oo2) and (21<oo2)) or (oo1=oo2));
mem(22)<=mem_line when (guard='1') and (((oo1<=22) and (22<oo2)) or ((oo1>oo2) and (22<oo2)) or (oo1=oo2));
mem(23)<=mem_line when (guard='1') and (((oo1<=23) and (23<oo2)) or ((oo1>oo2) and (23<oo2)) or (oo1=oo2));
oo<=conv_integer(ora);
mem_ora<=mem(oo);
t1(5)<=mem_ora(11);
t1(4)<=mem_ora(10);
t1(3)<=mem_ora(9);
t1(2)<=mem_ora(8);
t1(1)<=mem_ora(7);
t1(0)<=mem_ora(6);
t2(5)<=mem_ora(5);
t2(4)<=mem_ora(4);
t2(3)<=mem_ora(3);
t2(2)<=mem_ora(2);
t2(1)<=mem_ora(1);
t2(0)<=mem_ora(0);
temp_min<=t2;
temp_max<=t1;
end architecture struct;
这里是错误： enter image description here
内存中每一行的错误ar。
你是对的我没有解释组件应该做什么。
我想在nexys 4 fpga上实现我的代码作为一个大学项目，该项目是描述一个公寓的恒温器，恒温器需要有一个数字时钟，并能够设置每小时最小和最高温度的间隔。这个组件（c4：UMDT）是我24小时内每个温度区间记忆的地方。间隔的集合由这个图表给出，我们有o1，o2，t_min，t_max，存储器应该写在小时o1和o2之间，最低温度是t_min，最高温度是t_max
“plus”，“minus”和“ok”是按钮输入
答案 0 :(得分：1)
嗯......错误信息非常清楚。在几乎所有行中都有不完整的when / else语句，您可以在其中为内存分配内容。例如：
mem(1)<=mem_line when (guard='1') and (((oo1<=1) and (1<oo2)) or ((oo1>oo2) and (1<oo2)) or (oo1=oo2));
但是你没有提供任何关于你的设计的解释，所以我无法判断它是否只是错误的。我有一种感觉，这部分应该以其他方式完成。
我还要指出三件事：
okay进程中想要实现的目标，但您可能需要将okk信号添加到敏感列表中。