Question

我正在使用modelsim。我写了简单的代码，但我收到了错误。

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;



entity clk_counter is
port(output    : out   bit;
     clk : in bit
   );
end clk_counter;

architecture rtl of clk_counter_arch is

    signal clock_counter_output_flag: bit;
    constant clock_max_count : integer := 20000;


begin

     process (clock_counter_output_flag, clk,CLK'event )

       variable clock_count : integer := 0; 
       --constant clock_max_count : integer := 20000;
       variable clock_out : bit := 0;
       -- wait until CLK'event and CLK='1';
          begin
              if (CLK'event and CLK='1') then
                  clock_count := clock_count+1;
                  if (clock_count = clock_max_count) then
                      clock_out := 1;
                   else
                       clock_out := 0;  
                  end if
               end if
               clock_counter_output_flag <= clock_out;        
          end process;


END Architecture;

错误消息：

 # ** Error: (vcom-11) Could not find work.clk_counter_arch.                    
 #                                                                         
 # ** Error: C:/Modeltech_pe_edu_10.4a/examples/work/src/clk_counter(13):              VHDL Compiler exiting

Answer 1

您的实体名称是clk_counter，您已经定义了clk_counter_arch的架构rtl。因此，你会收到错误。将clk_counter_arch更改为clk_counter。

其次，你应该将架构作为结束rtl结束。

另外，为什么要使用另外两个变量clock_out和clock_counter_output_flag？如果您希望将这些值作为代码的输出，则只需编写

即可

if (CLK'event and CLK='1') then
                  clock_count := clock_count+1;
                  if (clock_count = clock_max_count) then
                      output<='1';
                   else
                       output <='0';  
                  end if;
               end if;

错误：VHDL编译器退出

1 个答案: