Question

自我介绍VHDL课程已经2年了，我需要在VHDL上刷新自己现在的课程项目。我开始构建一个4位CLA加法器，并且正在开发一个测试平台。我收到以下错误，我不知道为什么。我很确定这应该是什么样子，但我的记忆可能会消失。请帮我。

哦，作为参考，错误发生在

的第一个信号声明上

错误：COMP96_0019：adder_tb.vhd：（45,53）：关键字“开始”预期。
错误：COMP96_0016：adder_tb.vhd：（45,54）：预期的设计单位声明。

我的测试平台代码：

1

ibrary IEEE;
use IEEE.STD_LOGIC_1164.all;

entity adder_tb is   
end adder_tb;

architecture behavior of adder_tb is 
    -- Initialize the inputs/outputs of the unit to be tested
    component cl_adder_4bit
        port(
            a : in std_logic_vector(3 downto 0);
            b : in std_logic_vector(3 downto 0) ;
            c_in : in std_logic := '0';
            sum : out std_logic_vector(3 downto 0);
            c_out : out std_logic
        );
    end component;

-- Signal declarations for stimulation    
    signal a : std_logic_vector(3 downto 0) := "0000";  //initial value will be 0;
    signal b : std_logic_vector(3 downto 0) := "0000";
    signal c_in : std_logic;
    signal sum : std_logic_vector(3 downto 0);
    signal c_out : std_logic;

begin 
    uut: cl_adder_4bit port map(
        a <= a;
        b <= b;
        c_in <= c_in; 
        sum <= sum;
        c_out <= c_out;
    );              

    stimulate: process
    begin        
        --This loop is for when c_in = 0
        for i in 0 to 15 loop         
            -- This loop increments vector signal a, starting at b = 0x0
            for j in 0 to 15 loop
                wait for 5 ns;  //wait for 5 ns
                a <= a + 1;
            end loop; 
            -- This loop increments vector signal b, starting at a = 0xF
            for k in 0 to 15 loop
                wait for 5 ns; 
                b <= b + 1;
            end loop;
            a <= a + 1;
            b <= b + 1;
        end loop;
        --This second run is for when c_in is 1
        for i in 0 to 15 loop
            c_in <= '1';
            -- This loop increments vector signal a, starting at b = 0x0
            for j in 0 to 15 loop
                wait for 5 ns;  //wait for 5 ns
                a <= a + 1;
            end loop; 
            -- This loop increments vector signal b, starting at a = 0xF
            for k in 0 to 15 loop
                wait for 5 ns; 
                b <= b + 1;
            end loop;
            a <= a + 1;
            b <= b + 1;
        end loop;
    end process;

end adder_tb;

Answer 1

怎么样

signal a : std_logic_vector(3 downto 0) := "0000";  //initial value will be 0;

应使用VHDL评论指示：

signal a : std_logic_vector(3 downto 0) := "0000";  -- initial value will be 0;

或者你的评论无论如何都有点多余。

逗号作为分隔符并且您在端口映射中关联元素：

uut: cl_adder_4bit port map(
    a <= a;
    b <= b;
    c_in <= c_in; 
    sum <= sum;
    c_out <= c_out;
);

应该是：

uut: cl_adder_4bit port map(
    a => a,
    b => b,
    c_in => c_in, 
    sum => sum,
    c_out => c_out
);

另一个错误的评论分隔：

        wait for 5 ns;  //wait for 5 ns

应该是：

        wait for 5 ns;  -- wait for 5 ns

（以上两地）

架构的结束语句：

end adder_tb;

应该是：

end architecture;

或

end architecture behavior;

或

end behavior;

然后因为您正在使用添加运算符，您需要一个带有适当包的use子句，在这种情况下看起来它应该是Synopsys的std_logic_unsigned（in），方便地隐藏在库ieee中：

（在设计文件的顶部）：

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

初学者的VHDL错误

1 个答案: