VHDL编译器退出

时间:2016-06-25 21:06:36

标签: vhdl test-bench

我只想运行测试台,但我得到了这个。谁知道为什么?这是一个简单的代码。

总是有哪些测试台:

LIBRARY ieee;                                               
USE ieee.std_logic_1164.all;                                

ENTITY serpar3_vhd_tst IS
END serpar3_vhd_tst;
ARCHITECTURE serpar3_arch OF serpar3_vhd_tst IS
-- constants

给予" periodo"值20ns:

constant periodo: time:= 20ns

给一些变量一个起始值:

-- signals                                                   
SIGNAL a : STD_LOGIC;
SIGNAL b : STD_LOGIC;
SIGNAL c : STD_LOGIC;
SIGNAL clk : STD_LOGIC:='0';
SIGNAL rst : STD_LOGIC:='1';
SIGNAL x : STD_LOGIC:='1';
COMPONENT serpar3
    PORT (
    a : OUT STD_LOGIC;
    b : OUT STD_LOGIC;
    c : OUT STD_LOGIC;
    clk : IN STD_LOGIC;
    rst : IN STD_LOGIC;
    x : IN STD_LOGIC
    );
END COMPONENT;
BEGIN
    i1 : serpar3
    PORT MAP (
-- list connections between master ports and signals
    a => a,
    b => b,
    c => c,
    clk => clk,
    rst => rst,
    x => x
    );

重置过程:

init : PROCESS
BEGIN                                                        
wait for periodo;
rst<=not(rst);        -- code that executes only once                      
WAIT;                                                       
END PROCESS init;

时钟流程:

always : PROCESS      BEGIN                                                         
wait for periodo*0.5;
clk<=not(clk);                                                  
END PROCESS always;                                          

给予&#34; x&#34;一些价值观:

xpr: process
begin
wait for periodo;
x<='1';
wait for periodo;
x<='1';
wait for periodo;
x<='0';
wait for periodo;
x<='1';
wait for periodo;
x<='0';
end process xpr;
END serpar3_arch;

错误消息:

# ** Error: C:/Users/EDUARDO/Documents/PUCP/2016-1/Circuitos Digitales/Random VHDL/serpar3/simulation/modelsim/serpar3.vht(91): VHDL Compiler exiting
# ** Error: C:/altera/13.1/modelsim_ase/win32aloem/vcom failed.

0 个答案:

没有答案