VHDL错误信号

Question

我试图做一个数字时钟，但只在模拟器中，我不需要在FPGA板上测试它。我不需要使用时钟来改变秒数。

begin  
an <= random_gen(2000, 2017); 
luna<= random_gen(1,12);
temp<=random_gen(-15, 35);

process(ora)
begin
    if mounth = 9 or mounth = 4 or mounth =6 or mounth = 11 then
        day<=random_gen(1,30);
    elsif mounth = 1 or mounth = 3 or mounth = 5 or mounth = 7 or mounth = 8 or mounth = 9 or mounth = 10 or mounth = 12 then
        day<=random_gen(1,31);
    elsif mounth = 2 and (an = 2000 or an = 2004 or an = 2008 or an = 2012 or an = 20016) then
        day<=random_gen(1,28);
    else day<=random_gen(1,29);
    end if;    
end process;

hour<=random_gen(1,23);
min<=random_gen(1,59);
sec<=random_gen(1,59);

process(sec)
begin
    sec<=sec+1;
        if(sec = 59) then
            sec<=0;
            min <= min + 1;
            if(min = 59) then
                hour <= hour + 1;
                min <= 0;
                if(hour = 23) then
                    hour <= 0;
                end if;
            end if;
        end if;
end process;
end architecture;

我得到的错误是：信号“sec”有两个来源，但未解析信号。

我也得到“min”和“hour”