Question

我为vga控制器创建了这个代码，模拟也是正确的。问题是当代码运行时监视器是空白的，同样在波形生成中显示两个输出的hsync和vsync＆＃39; 0＆＃39;。我不知道逻辑出错的地方。请帮忙。

代码：

module anymodule(input wire clk,reset,
output wire hsynch,vsynch,
output [2:0] red,
output [2:0] green,
output [1:0] blue,
output video_on);


// defining constants
localparam HD = 800; // horizontal display area
localparam HF = 56; // front porch (right border)
localparam HB = 64; //right porch (left border)
localparam HR = 120; // horizontal retrace
localparam VD = 600; // vertical display area
localparam VF = 37; // front porch (bottom border)
localparam VB = 23; // back porch (top border)
localparam VR = 6; // vertical retrace



//horizontal and vertical counter
reg  [9:0] h_count = 0;
reg  [9:0] v_count = 0;
wire [9:0] h_end,v_end;

assign h_end = HD+HF+HR+HB-1;
assign v_end = VD+VF+VR+VB-1;


always @(*) begin
  if(clk)
    if(h_end)
      h_count = 0;
    else
      h_count = h_count+1;
  else
    h_count = h_count;
end

always @(posedge clk) begin
  if(h_end) 
     if(v_count<v_end)
       v_count = v_count+1;
     else
       v_count = 0;
  else
    v_count = v_count;
end

assign hsynch   = ((h_count >= HD+HF-1) && (h_count <= HD+HF+HR+HB-1));
assign vsynch   = ((v_count >= VD+VF-1) && (v_count <= VD+VF+VR+VB-1));
assign video_on = ((h_count <  HD)      && (v_count <  VD));

wire [9:0] pixel_x,pixel_y;
assign pixel_x = (video_on)? h_count : 10'b0;
assign pixel_y = (video_on)? v_count : 10'b0;


reg [7:0] coloroutput;

always @(clk)
  if(~video_on)
    coloroutput <= 0;
  else begin
    if( pixel_x<150 && pixel_y<160)
      coloroutput[7:5] <= 3'b111;
    else if(pixel_x<250 && pixel_y<320)
      coloroutput[4:2] <= 3'b111;
    else
      coloroutput[1:0] <= 2'b11;
  end


assign red   = (video_on) ? coloroutput[7:5] : 3'b000;
assign green = (video_on) ? coloroutput[4:2] : 3'b000;
assign blue  = (video_on) ? coloroutput[1:0] : 3'b000;


endmodule

Answer 1

你一定要尝试模拟这个。我很确定你会发现你的代码在模拟中不起作用。在尝试编程FPGA之前，请务必在仿真环境中检查代码！你有这一行：

always @(*) begin
  if(clk)
    if(h_end)
      h_count = 0;

h_end是一个静态值，你需要将它与某些东西进行比较。也许：

if (h_count == h_end)

这样的事情。此外，这个始终阻止应该告诉工具寻找时钟信号的上升沿。 E.g。

always @(posedge clk) begin
  if (h_count == h_end)

查询：显示器上无显示（VGA CONTROLLER 800 * 600分辨率）BASYS 2 BOARD

1 个答案: