Question

我正在使用Spartan 6 Posedge One开发板，其基本时钟为：24MHz，以便使用VGA verilog模块和开发板上的VGA电缆在监视器上显示简单的图像。我在使用VGA 640x480p之前已经做到了这一点，但是现在我将分辨率更改为1024x768，时钟为：75MHz，什么也没显示。

由于基本时钟为24MHz，因此使用Clocking向导v3.6 IP Core生成了75MHz时钟，并将其命名为CGM（时钟发生器模块）。并且已经检查了hsync，vsync等的时间，但仍未在监视器上显示任何内容。更换了主板，VGA电缆，但仍然没有结果。甚至更改了vsync和hsync的极性，但仍然没有改变。（我得到警告“组件clk_wiz_v3_6没有用于Verilog合成的有效模型名称”，但它似乎并未影响我的项目。没有尝试更改名称。虽然是“ CGM” ...）

`timescale 1ns / 1ps
module VGA(
input  wire i_clk,          // clock: 75MHz
input  wire i_rst,          // reset: restarts frame
output wire o_hs,           // horizontal sync
output wire o_vs,           // vertical sync
output wire o_blanking,     // high during blanking interval
output wire o_active,       // high during active pixel drawing
output wire o_screenend,    // high for one tick at the end of screen
output wire o_animate,      // high for one tick at end of active drawing
output wire [10:0] o_x,     // current pixel x position
output wire [9:0] o_y       // current pixel y position
);

localparam HS_STA = 24;              // horizontal sync start
localparam HS_END = 24 + 136;        // horizontal sync end
localparam HA_STA = 24 + 136 + 144;  // horizontal active pixel start
localparam VS_STA = 768 + 3;         // vertical sync start
localparam VS_END = 768 + 3 + 6;     // vertical sync end
localparam VA_END = 768;             // vertical active pixel end
localparam LINE   = 1328;            // complete line (pixels)
localparam SCREEN = 806;             // complete screen (lines)

reg [10:0] h_count; // line position
reg [9:0] v_count;  // screen position

// generate sync signals (active low)
assign o_hs = ~((h_count >= HS_STA) & (h_count < HS_END));
assign o_vs = ~((v_count >= VS_STA) & (v_count < VS_END));

// keep x and y bound within the active pixels
assign o_x = (h_count < HA_STA) ? 0 : (h_count - HA_STA);
assign o_y = (v_count >= VA_END) ? (VA_END - 1) : (v_count);

// blanking: high within the blanking period
assign o_blanking = ((h_count < HA_STA) | (v_count > VA_END - 1));

// active: high during active pixel drawing
assign o_active = ~((h_count < HA_STA) | (v_count > VA_END - 1)); 

// screenend: high for one tick at the end of the screen
assign o_screenend = ((v_count == SCREEN - 1) & (h_count == LINE));

// animate: high for one tick at the end of the final active pixel line
assign o_animate = ((v_count == VA_END - 1) & (h_count == LINE));

always @ (posedge i_clk)
begin
    if (i_rst)  // reset to start of frame
    begin
        h_count <= 0;
        v_count <= 0;
    end
    else
    begin
        if (h_count == LINE)  // end of line
        begin
            h_count <= 0;
            v_count <= v_count + 1;
        end
        else 
            h_count <= h_count + 1;

        if (v_count == SCREEN)  // end of screen
            v_count <= 0;
    end
end
endmodule

//Monitor

module MONITOR(
input  wire CLK,            // clock: 75 MHz
input  wire RST_BTN,        // reset button
output wire VGA_HS_O,       // horizontal sync output
output wire VGA_VS_O,       // vertical sync output
output wire [1:0] VGA_R,    // 2-bit VGA red output
output wire [1:0] VGA_G,    // 2-bit VGA green output
output wire [1:0] VGA_B     // 2-bit VGA blue output
);

wire rst = ~RST_BTN;    // reset is active low

wire [10:0] x;  // current pixel x position: 10-bit value: 0-1023
wire [9:0] y;   // current pixel y position:  9-bit value: 0-511

VGA Display (
    .i_clk(CLK),
    .i_rst(rst),
    .o_hs(VGA_HS_O), 
    .o_vs(VGA_VS_O), 
    .o_x(x), 
    .o_y(y)
);

// Four overlapping squares
wire [1:0] sq_a, sq_b, sq_c, sq_d;
assign sq_a = ((x > 310) & (y >  40) & (x < 470) & (y < 200)) ? 2'b11 : 2'b00; 
assign sq_b = ((x > 390) & (y > 120) & (x < 550) & (y < 280)) ? 2'b11 : 2'b00;
assign sq_c = ((x > 470) & (y > 200) & (x < 630) & (y < 360)) ? 2'b11 : 2'b00;
assign sq_d = ((x > 550) & (y > 280) & (x < 710) & (y < 440)) ? 2'b11 : 2'b00;

assign VGA_R = sq_b;         // square b is red
assign VGA_G = sq_a | sq_d;  // squares a and d are green
assign VGA_B = sq_c;         // square c is blue
endmodule


//TOP MODULE

module BOARD(
input clk,
input rst,
output wire VGA_HS_O,       // horizontal sync output
    output wire VGA_VS_O,       // vertical sync output
    output wire [1:0] VGA_R,    // 2-bit VGA red output
    output wire [1:0] VGA_G,    // 2-bit VGA green output
    output wire [1:0] VGA_B     // 2-bit VGA blue output
   );

CGM Clock(
     .CLK_IN1(clk),
     .CLK_OUT1(CLK_OUT1),     
     .RESET(rst)
     ); 

MONITOR Monitor (
     .CLK(CLK_OUT1), 
     .RST_BTN(rst), 
     .VGA_HS_O(VGA_HS_O), 
     .VGA_VS_O(VGA_VS_O), 
     .VGA_R(VGA_R), 
     .VGA_G(VGA_G), 
     .VGA_B(VGA_B)
     );
endmodule

我希望在屏幕上看到四个具有不同颜色的重叠正方形。如果有FPGA板的人能测试我的代码，我将非常感谢。顺便说一句，这些代码被写在三个不同的.v文件中，而不是在同一个.v文件中。我把所有的东西都带给你们大家看看。

VGA使用Xilinx Spartan 6 Posedge One板在显示器上显示黑屏

0 个答案: