Question

我在VGA控制器（Basys 2板）中加入时钟分频器（40 MHz）时出错。编码出错 - 输入缓冲区instance_name / CLKIN_IBUFG_INST的端口I连接到GND。请帮忙删除此错误！

代码如下：

module anymodule(input wire clk,reset,
output wire hsynch,vsynch,
output [2:0] red,
output [2:0] green,
output [1:0] blue,
output video_on);


// defining constants
localparam HD = 800; // horizontal display area
localparam HF = 40; // front porch (right border)
localparam HB = 88; //right porch (left border)
localparam HR = 128; // horizontal retrace
localparam VD = 600; // vertical display area
localparam VF = 1; // front porch (bottom border)
localparam VB = 23; // back porch (top border)
localparam VR = 4; // vertical retrace

wire pixel_tick;


//clock divider

// Instantiate the module
clkdiv instance_name (
    .CLKIN_IN(CLKIN_IN), 
    .RST_IN(RST_IN), 
    .CLKFX_OUT(pixel_tick), 
    .CLKIN_IBUFG_OUT(CLKIN_IBUFG_OUT), 
    .CLK0_OUT(CLK0_OUT), 
    .LOCKED_OUT(LOCKED_OUT)
    );




//horizontal and vertical counter

reg [9:0] h_count = 0;
reg [9:0] v_count = 0;
wire [9:0] h_end,v_end;

assign h_end = HD+HF+HR+HB-1;
assign v_end = VD+VF+VR+VB-1;


always @(pixel_tick)
if(h_count<h_end)
h_count <= h_count+1;
else
h_count <= 0;


always @(*)
if(pixel_tick & h_end)
if(v_count<v_end)
v_count <= v_count+1;
else
v_count <= 0;
else
v_count <= v_count;


assign hsynch = ((h_count>= HD+HF-1) && (h_count<=HD+HF+HR+HB-1));
assign vsynch = ((v_count>=VD+VF-1) && (v_count<= VD+VF+VR+VB-1));
assign video_on = ((h_count <HD) && (v_count<VD));

wire [9:0] pixel_x,pixel_y;
assign pixel_x = (video_on)? h_count : 'b0;
assign pixel_y = (video_on)? v_count : 'b0;


reg [7:0] coloroutput;


always @(pixel_tick)
if(~video_on)
coloroutput <= 0;
else
begin
if(pixel_y<160)
coloroutput[7:5] <= 3'b111;
else if(pixel_y<320)
coloroutput[4:2] <= 3'b111;
else
coloroutput[1:0] <= 2'b11;
end


assign red = (video_on)?coloroutput[7:5] : 3'b000;
assign green = (video_on)?coloroutput[4:2] : 3'b000;
assign blue = (video_on)?coloroutput[1:0] : 3'b000;


endmodule

Answer 1

搜索代码CLKIN_IN它只显示在下一行，这意味着没有任何驱动它，即连接到地（GND）。

// Instantiate the module
clkdiv instance_name (
    .CLKIN_IN(CLKIN_IN),  //<-- Not connected

如果变量未被声明为logic / wire / reg / tri等，则暗示1位线路，因此您无法获得未连接端口的类型检查，但是它是未驱动的。模拟应该将其显示为Z驱动。

查询：VGA控制器（Verilog）Basys 2板中使用的时钟分频器出错

1 个答案: