Question

我想在Xilinx Vivado 2017.4中使用Verilog HDL设计一个4位向上计数器，并希望使用BASYS 3（Artix 7）板显示结果。模拟结果运行良好，但是当我在Basys 3板上下载比特流时，LED指示灯不发光。计数器的主要代码及其约束文件如下。帮助我解决问题，以便Basys 3 FPGA板的LED正确发光。

// the main module of counter
`timescale 1ns / 1ps
module count(clk,rst,en,q);
input clk,rst,en;
output [7:0] q;
reg [7:0] q;
always @(posedge clk)
begin 
if (rst)
begin
q=0;
end
if(en)
begin
q<=q+1;
//$display(q);
end
else 
begin
q<=q;
end
end
endmodule

约束文件：

## Clock signal
set_property PACKAGE_PIN W5 [get_ports clk]                         
    set_property IOSTANDARD LVCMOS33 [get_ports clk]
    create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports clk]


set_property PACKAGE_PIN V17 [get_ports {rst}]                  
    set_property IOSTANDARD LVCMOS33 [get_ports {rst}]
set_property PACKAGE_PIN V16 [get_ports {en}]                   
    set_property IOSTANDARD LVCMOS33 [get_ports {en}]
set_property PACKAGE_PIN U16 [get_ports {q[0]}]                 
    set_property IOSTANDARD LVCMOS33 [get_ports {q[0]}]
set_property PACKAGE_PIN E19 [get_ports {q[1]}]                 
    set_property IOSTANDARD LVCMOS33 [get_ports {q[1]}]
set_property PACKAGE_PIN U19 [get_ports {q[2]}]                 
    set_property IOSTANDARD LVCMOS33 [get_ports {q[2]}]
set_property PACKAGE_PIN V19 [get_ports {q[3]}]                 
    set_property IOSTANDARD LVCMOS33 [get_ports {q[3]}]
set_property PACKAGE_PIN W18 [get_ports {q[4]}]                 
    set_property IOSTANDARD LVCMOS33 [get_ports {q[4]}]
set_property PACKAGE_PIN U15 [get_ports {q[5]}]                 
    set_property IOSTANDARD LVCMOS33 [get_ports {q[5]}]
set_property PACKAGE_PIN U14 [get_ports {q[6]}]                 
    set_property IOSTANDARD LVCMOS33 [get_ports {q[6]}]
set_property PACKAGE_PIN V14 [get_ports {q[7]}]                 
    set_property IOSTANDARD LVCMOS33 [get_ports {q[7]}]

我的FPGA BASYS 3板未显示输出？

0 个答案: