Question

我的代码中出现了一个奇怪的错误，编译得很好，但我一直收到警告：

警告：未连接，内部信号\ s（0）D \被提升为输入PIN。

警告：未连接，内部信号\ s（1）D \被提升为输入PIN。

代码用于复位的基本寄存器，向左移位并插入S_IN，并使用Pload将设置的值加载到寄存器中。任何人都可以帮我弄清楚它有什么问题吗？

library IEEE;
use ieee.std_logic_1164.all;

entity special_register is
port( DATA:                 in    std_logic_vector(3 downto 0);     
    Reset:                  in    std_logic;
    PLoad:                  in    std_logic;
    S_Right:                in    std_logic;
    S_IN:                   in    std_logic;
    clock :                 in    std_logic;
    S:                      in    std_logic_vector(1 downto 0);
    D:                      out   std_logic_vector(3 downto 0);
    Q :                     out   std_logic_vector(3 downto 0));
end special_register;

architecture behav of special_register is
begin
process(clock, data, Reset, S_IN, S, S_Right, PLoad)
begin
if rising_edge(clock) then
S(0) <= (S_Right);
S(1) <= (PLoad);
if (S(1) = '1') then
    D(3) <= DATA(3);
    D(2) <= DATA(2);
    D(1) <= DATA(1);
    D(0) <= DATA(0);
else if (S(0) = '0') then
    D(0) <= Q(1);
    D(1) <= Q(2);
    D(2) <= Q(3);
    D(3) <= S_IN;       
end if;
end if;
end if;
end process;
Q(3) <= (NOT Reset) AND D(3);
Q(2) <= (NOT Reset) AND D(2);
Q(1) <= (NOT Reset) AND D(1);
Q(0) <= (NOT Reset) AND D(0);
end behav;

Answer 1

除了Brian的回答，你还可以注意到这个设计规范不符合VHDL，推测的综合工具也不是：

ghdl -a special_register.vhdl special_register.vhdl:21:2: port "s" can't be assigned special_register.vhdl:22:2: port "s" can't be assigned special_register.vhdl:29:14: port "q" cannot be read special_register.vhdl:30:14: port "q" cannot be read special_register.vhdl:31:14: port "q" cannot be read special_register.vhdl:37:26: port "d" cannot be read special_register.vhdl:38:26: port "d" cannot be read special_register.vhdl:39:26: port "d" cannot be read special_register.vhdl:40:26: port "d" cannot be read ghdl: compilation error

（看起来你也试图读取输出端口。）

在vhdl代码中获取警告错误

1 个答案: