Question

我是vhdl的新手。我有一个代码与我如下（子编程编译非常好）。我无法修复以下错误

**错误：C：/ Users / acer / Desktop / alu new / ALU_VHDL.vhd（110）：非法顺序语句。 **错误：C：/ Users / acer / Desktop / alu new / ALU_VHDL.vhd（115）：非法顺序语句。 **错误：C：/ Users / acer / Desktop / alu new / ALU_VHDL.vhd（120）：非法顺序语句。 **错误：C：/ Users / acer / Desktop / alu new / ALU_VHDL.vhd（128）：非法顺序语句。 **警告：[14] C：/ Users / acer / Desktop / alu new / ALU_VHDL.vhd（128）:( vcom-1272）正式“剩余”的长度为4;实际长度是8。

**错误：C：/ Users / acer / Desktop / alu new / ALU_VHDL.vhd（138）：VHDL编译器退出

这里的代码中的行号为粗体。它们是 portmap 任何人都可以帮我解决这个问题。你真好。

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity ALU_VHDL is
   port
   (
      OperandA : in std_logic_vector(3 downto 0);
      OperandB : in std_logic_vector(3 downto 0);
      Operation: in std_logic_vector(2 downto 0);
        Startt    : in std_logic;
      Ready : out std_logic;
        Result_High : out std_logic_vector(3 downto 0);
        Result_Low : out  std_logic_vector(7 downto 0);
        Errorsig : out std_logic;
        Reset_n : in std_logic;
        Clkk : in std_logic);
end entity ALU_VHDL;

architecture Behavioral of ALU_VHDL is
-- And gate
 component AND_gate
  port( 
    x,y  : IN std_logic_vector(3 downto 0);
    z    : OUT std_logic_vector(3 downto 0));
end component;

-- OR Gate
component OR_gate
  port( 
    x,y  : IN std_logic_vector(3 downto 0);
    z    : OUT std_logic_vector(3 downto 0));
end component;
-- XOR gate

component XOR_gate
  port( 
    x,y  : IN std_logic_vector(3 downto 0);
    z    : OUT std_logic_vector(3 downto 0));
end component;
-- Adder

COMPONENT adder4 
PORT
    (
    C : IN std_logic;
    x,y : IN std_logic_vector(3 DOWNTO 0);
    R   : OUT std_logic_vector(3 DOWNTO 0);
    C_out   : OUT std_logic);
END COMPONENT;

-- Subtractor
COMPONENT Substractor4 
PORT
       (
        br_in : IN std_logic;
        x,y : IN std_logic_vector(3 DOWNTO 0);

        R   : OUT std_logic_vector(3 DOWNTO 0);
        E   : out std_logic);
END COMPONENT;

-- Multiplier
COMPONENT mult4by4 
    port(operA, operB: in std_logic_vector(3 downto 0);
     sumOut: out std_logic_vector(7 downto 0));
END COMPONENT;

-- Division
COMPONENT Division 
Port ( Dividend : in std_logic_vector(3 downto 0);
           Divisor : in std_logic_vector(3 downto 0);
           Start :   in std_logic;
           Clk :     in std_logic;
           Quotient :  out std_logic_vector(3 downto 0);
           Remainder :    out std_logic_vector(3 downto 0);
           Finish : out std_logic);
END COMPONENT;  

 begin

   process(OperandA, OperandB, Startt, Operation) is
   begin


      case Operation is

             when "000" => 
                 Result_High <= "XXXX";


             when "001" =>
                 Result_High <= OperandA and OperandB;


                 when "010" =>
           Result_High <= OperandA or OperandB;


           when "011" =>
           Result_High <= OperandA xor OperandB;



           when "100" => 
           -- Adder
                 **U05 : adder4 PORT MAP (C=>Startt,x=>OperandA,y=>OperandB,R=>Result_High,C_out=>Ready);**


           when "101" =>
           -- Substractor & Error signal
                 **U06 : Substractor4 PORT MAP (br_in=>Startt,x=>OperandA,y=>OperandB,R=>Result_High,E=>Errorsig);**


             when "110" =>
                 -- multiplication
           **U07 : mult4by4 PORT MAP (operA=>OperandA,operB=>OperandB,sumOut=>Result_Low);**


           when "111" =>
                 -- Division
                 if (OperandB ="0000") then
                   Errorsig <= '1';
                 else
             **U08 : Division PORT MAP (Dividend=>OperandA,Divisor=>OperandB,Start=>Startt,Clk=>Clkk,Quotient=>Result_High,Remainder=>Result_Low,Finish=>Ready);**
                 end if;

                 when others =>
                 Errorsig <= '1';

      end case;

   end process;

end architecture Behavioral;

Answer 1

您无法在流程中实例化实体。

将所有实体实例移出进程（进入体系结构体）并从那里开始工作。

Answer 2

如果你想根据'Operation'的值实例化组件，就像zennehoy写的那样，你应该在进程中实例化组件，在这种情况下语句只使用在实例化中连接到这个组件的信号并将其链接到你想要的港口。

Answer 3

对于长度问题，更改＆＃34;剩余：输出std_logic_vector（3 downto 0）;＆＃34; to＆＃34; Remainder：out std_logic_vector（7 downto 0）;＆＃34;

vhdl代码中的错误

3 个答案: