Question

我正在尝试编写一个vhdl代码，它给了我更多的尝试为5个状态（S0，S1，S2，S3，S4）的顺序编写代码

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity Seqq is
PORT ( seq , clk , reset : IN std_logic;
       output : OUT std_logic;
         leds : OUT std_logic_vector( 2 downto 0) );
end Seqq;


architecture Behavioral of Seqq is
type states IS ( S0 , S1 , S2 , S3 , S4);
signal nxt , prst : states ;
begin
FB:PROCESS(reset, clk)
begin
if Rising_edge(clk) then
 if reset = '1' then prst <='0';

else prst <= nxt ;
end if ;
end if ;
end process FB;comb:PROCESS( prst) 
begin 
case prst IS 
when S0 =>
If seq = '0' then nxt <= S0;
elsif seq = '1' then nxt <= S1;
end if ;
leds <= "000";
output <= '0';

when S1 =>
If seq = '0' then nxt <= S2;
elsif seq = '1' then nxt <= S1;
end if ;
leds <= "001";
output <= '0';

when S2 =>
If seq = '0' then nxt <= S2;
elsif seq = '1' then nxt <= S1;
end if ;
leds <= "010";
output <= '0';

when S3 =>
If seq = '0' then nxt <= S0;
elsif seq = '1' then nxt <= S4;
end if ;
leds <= "011";
output <= '0';

when S4 =>
If seq = '0' then nxt <= S0;
output <= '1';
elsif seq = '1' then nxt <= S1;
end if ;
leds <= "100";
output <= '0';
end case ;
end process comb;


end Behavioral;

我得到的错误是

Type of prst is incompatible with type of '0'.

我该怎么办？

Answer 1

在这一行

if reset = '1' then prst <='0';

您正在为第一个分配'0'。如果您查看错误消息prst is incompatible with type of '0'，您会发现这些类型不匹配。

调查您的prst类型，您会看到它的类型为states，枚举范围为S0到S4。＆＃39; 0＆＃39;但是类型为std_logic或bit，不能转换为state。

所以，您可能想要的（如果您的逻辑仍然可以）是将prst的分配更改为S0：

if reset = '1' then prst <= S0;

Xilinx VHDL代码错误

1 个答案: