我是VHDL语言的新手。我正在尝试使用4：1 mux和D触发器编写通用移位寄存器。当4：1多路复用器的选择线为“01”时，我做右移操作。我编写了满足此条件时必须执行的所有语句。
我在我的代码中使用4：1多路复用器的实例。当每个多路复用器测试时，输出正确。但是当放入通用移位寄存器的if语句时，mux的输出在模拟时仍然表示未定义。 / p>
任何人都可以帮助我吗？
以下是我的代码
entity universal_sft_reg is
Port ( serial_in_left_ip : in STD_LOGIC;
serial_in_rt_ip : in STD_LOGIC;
parallel_ip : in STD_LOGIC_VECTOR (7 downto 0);
parallel_out : out STD_LOGIC_VECTOR (7 downto 0);
serial_out : out STD_LOGIC;
clk : in STD_LOGIC;
rst : in STD_LOGIC;
sel : in STD_LOGIC_VECTOR (1 downto 0));
end universal_sft_reg;
architecture Behavioral of universal_sft_reg is
component four_one_mux is
Port ( in0 : in STD_LOGIC;
in1 : in STD_LOGIC;
in2 : in STD_LOGIC;
in3 : in STD_LOGIC;
s0 : in STD_LOGIC;
s1 : in STD_LOGIC;
y : out STD_LOGIC);
end component;
component DFF is
Port ( d : in STD_LOGIC;
q : out STD_LOGIC;
rst : in STD_LOGIC;
clk : in STD_LOGIC);
end component;
signal d1,d2,d3,d4,d5,d6,d7,d8 : STD_LOGIC;
signal y1,y2,y3,y4,y5,y6,y7,y8 : STD_LOGIC; signal n0_1,in1_1,in2_1,in3_1,in0_2,in1_2,in2_2,in3_2,in0_3,in1_3,in2_3,in3_3,in0_4,in1_4,in2_4,in3_4,in0_5,in1_5,in2_5,in3_5,in0_6,in1_6,in2_6,in3_6,in0_7,in1_7,in2_7,in3_7,in0_8,in1_8,in2_8,in3_8 :STD_LOGIC;
signal q1,q2,q3,q4,q5,q6,q7,q8 : STD_LOGIC;
begin
DFF1 : DFF port map(d1,q1,rst,clk);
DFF2 : DFF port map(d2,q2,rst,clk); DFF3 : DFF port map(d3,q3,rst,clk);
DFF4 : DFF port map(d4,q4,rst,clk);
DFF5 : DFF port map(d5,q5,rst,clk); DFF6 : DFF port map(d6,q6,rst,clk);
DFF7 : DFF port map(d7,q7,rst,clk);
DFF8 : DFF port map(d8,q8,rst,clk);
MUX1 : four_one_mux port map(in0_1,in1_1,in2_1,in3_1,sel(0),sel(1),y1);
MUX2 : four_one_mux port map(in0_2,in1_2,in2_2,in3_2,sel(0),sel(1),y2);
MUX3 : four_one_mux port map(in0_3,in1_3,in2_3,in3_3,sel(0),sel(1),y3);
MUX4 : four_one_mux port map(in0_4,in1_4,in2_4,in3_4,sel(0),sel(1),y4);
MUX5 : four_one_mux port map(in0_5,in1_5,in2_5,in3_5,sel(0),sel(1),y5);
MUX6 : four_one_mux port map(in0_6,in1_6,in2_6,in3_6,sel(0),sel(1),y6);
MUX7 : four_one_mux port map(in0_7,in1_7,in2_7,in3_7,sel(0),sel(1),y7);
MUX8 : four_one_mux port map(in0_8,in1_8,in2_8,in3_8,sel(0),sel(1),y8);
process(clk,sel)
begin
if(clk = '1' and clk'event) then
if sel = "00" then
d1 <= y1;
d2 <= y2;
d3 <= y3;
d4 <= y4;
d5 <= y5;
d6 <= y6;
d7 <= y7;
d8 <= y8;
end if;
if( sel = "01") then
in1_8 <= serial_in_rt_ip;--input to the mux
--y8 is not getting updated with the input value!!!!.
d8 <= y8;
in1_7 <= q8;
d7 <= y7;
in1_6 <= q7;
d6 <= y6;
in1_5 <= q6;
d5 <= y5;
in1_4 <= q5;
d4 <= y4;
in1_3 <= q4;
d3 <= y3;
in1_2 <= q3;
d2 <= y2;
in1_1 <= q2;
d1 <= y1;
serial_out <= q1;
end if;
if( sel="10") then
in2_1 <= serial_in_left_ip;
d1 <= y1;
in2_2 <= q1;
d2 <= y2;
in2_3 <= q2;
d3 <= y3;
in2_4 <= q3;
d4 <= y4;
in2_5 <= q4;
d5 <= y5;
in2_6 <=q5;
d6 <= y6;
in2_7 <= q6;
d7 <= y7;
in2_8 <= q7;
d8 <= y8;
serial_out <= q8;
end if;
if(sel ="11") then
in3_1 <= parallel_ip(0);
in3_2 <= parallel_ip(1);
in3_3 <= parallel_ip(2);
in3_4 <= parallel_ip(3);
in3_5 <= parallel_ip(4);
in3_6 <= parallel_ip(5);
in3_7 <= parallel_ip(6);
in3_8 <= parallel_ip(7);
d1 <= y1;
d2 <= y2;
d3 <= y3;
d4 <= y4;
d5 <= y5;
d6 <= y6;
d7 <= y7;
d8 <= y8;
parallel_out(0) <= q1;
parallel_out(1) <= q2;
parallel_out(2) <= q3;
parallel_out(3) <= q4;
parallel_out(4) <= q5;
parallel_out(5) <= q6;
parallel_out(6) <= q7;
parallel_out(7) <= q8;
end if;
end if;
end process;
end Behavioral;
答案 0 :(得分：1)
鉴于您使用mux和dff编写移位寄存器的既定目标，您根本不应在移位寄存器设计中使用过程。
您应该能够直接连接8个DFF和MUX组件，以便获得移位寄存器。目前，您正在为流程创建其他（和冗余）MUX和DFF。
我建议让它工作：使用8个MUX和8个DFF绘制一个框图，然后编写VHDL来描述你的框图。