Verilog testbench for fifo

时间:2014-03-21 13:51:57

标签: verilog fifo icarus

任何人都可以帮我编写以下代码的verilog测试平台代码!  我试过但是它不起作用! 它是一个带有单个时钟的fifo(先进先出)代码。 我使用icarus模拟器

FIFO4:

`timescale 1ns/10ps

module fifo4(clk, rst, clr,  din, we, dout, re, full, empty);

parameter dw = 8;

input       clk, rst;
input       clr;
input   [dw:1]  din;
input       we;
output  [dw:1]  dout;
input       re;
output      full, empty;




reg     [dw:1]  mem[0:3];
reg     [1:0]   wp;
reg     [1:0]   rp;
wire    [1:0]   wp_p1;
wire    [1:0]   wp_p2;
wire    [1:0]   rp_p1;
wire        full, empty;
reg     gb;


always @(posedge clk or negedge rst)
    if(!rst)    wp <= #1 2'h0;
    else
    if(clr)     wp <= #1 2'h0;
    else
    if(we)      wp <= #1 wp_p1;

assign wp_p1 = wp + 2'h1;
assign wp_p2 = wp + 2'h2;

always @(posedge clk or negedge rst)
    if(!rst)    rp <= #1 2'h0;
    else
    if(clr)     rp <= #1 2'h0;
    else
    if(re)      rp <= #1 rp_p1;

assign rp_p1 = rp + 2'h1;


assign  dout = mem[ rp ];


always @(posedge clk)
    if(we)  mem[ wp ] <= #1 din;


assign empty = (wp == rp) & !gb;
assign full  = (wp == rp) &  gb;


always @(posedge clk)
if(!rst)            gb <= #1 1'b0;
else
if(clr)             gb <= #1 1'b0;
else
if((wp_p1 == rp) & we)      gb <= #1 1'b1;
else
if(re)              gb <= #1 1'b0;

endmodule

1 个答案:

答案 0 :(得分:1)

EDA Playground上使用Icarus模拟了RAM测试平台的示例,您可以将其作为起点:

  1. Verilog testbench
  2. Python testbench
  3. MyHDL design and testbench
  4. 从根本上说,您需要确定您要测试的内容,如何生成测试向量以执行FIFO以及如何验证您的FIFO是否按预期运行。后者在查看波形时可能很简单,但建立一个不需要手动检查的自检测试台要好得多。

    同样值得指出的是,在代码中使用#1延迟通常表明出现了问题。