Question

我是Verilog的新手，我需要在a等于，小于和大于b时制作一个8位比较器。这就是我对代码的看法（它没有给我任何错误）：

module MagnitudeComparator8bit (input signed [7:0]a,
                                input signed [7:0]b,
                                output eq,
                                output lt,
                                output gt);
    assign eq = a == b;
    assign lt = a < b;
    assign gt = a > b;
endmodule

这就是我对testbench所拥有的，但是当我运行模拟时，我遇到了多个错误，但我不确定我哪里出错了。有什么帮助吗？

module MagnitudeComparatorTestbench;
    reg [7:0] a, b;
    wire eq, lt, gt;

    MagnitudeComparator8bit uut(
       .a(a),
       .b(b),
       .eq(eq),
       .lt(lt),
       .gt(gt)
    );

    initial begin
          $monitor (“%d %b %b %d %d %d”, $time, a, b, eq, lt, gt);
          a=8’b11110000;
          b=8’b11110000;
      #10 a=8’b1001001;
          b=8’b10101010;
      #10 a=8’b11001100;
          b=8’b10101000;
      #10 $finish
   end  
endmodule

错误：

testbench.sv:14: error: unmatched character (hex ?)
testbench.sv:e: error: unmatched character (hex ?)
testbench.sv:e: error: unmatched character (hex ?)
testbench.sv:e: syntax error
testbench.sv:e: error: unmatched character (hex ?)
testbench.sv:e: error: unmatched character (hex ?)
testbench.sv:e: error: unmatched character (hex ?)
testbench.sv:e: error: malformed statement
testbench.sv:f: error: unmatched character (hex ?)
testbench.sv:f: error: unmatched character (hex ?)
testbench.sv:f: error: unmatched character (hex ?)
testbench.sv:f: syntax error
testbench.sv:f: error: malformed statement
testbench.sv:10: error: unmatched character (hex ?)
testbench.sv:10: error: unmatched character (hex ?)
testbench.sv:10: error: unmatched character (hex ?)
testbench.sv:10: syntax error
testbench.sv:10: error: malformed statement
testbench.sv:11: error: unmatched character (hex ?)
testbench.sv:11: error: unmatched character (hex ?)
testbench.sv:11: error: unmatched character (hex ?)
testbench.sv:11: syntax error
testbench.sv:11: error: malformed statement
testbench.sv:12: error: unmatched character (hex ?)
testbench.sv:12: error: unmatched character (hex ?)
testbench.sv:12: error: unmatched character (hex ?)
testbench.sv:12: syntax error
testbench.sv:12: error: malformed statement
testbench.sv:13: error: unmatched character (hex ?)
testbench.sv:13: error: unmatched character (hex ?)
testbench.sv:13: error: unmatched character (hex ?)
testbench.sv:13: syntax error
testbench.sv:13: error: malformed statement
testbench.sv:14: error: unmatched character (hex ?)
testbench.sv:14: error: unmatched character (hex ?)
testbench.sv:14: error: unmatched character (hex ?)
testbench.sv:14: syntax error
testbench.sv:14: error: malformed statement
testbench.sv:16: syntax error
Exit code expected: 0, received: 40

Answer 1

您的帖子中有奇怪的引号字符。复制并粘贴代码后，这些错误给了我错误。我修好了报价。复制此代码：

module MagnitudeComparatorTestbench;
    reg [7:0] a, b;
    wire eq, lt, gt;

    MagnitudeComparator8bit uut(
       .a(a),
       .b(b),
       .eq(eq),
       .lt(lt),
       .gt(gt)
    );

    initial begin
          $monitor ("%d %b %b %d %d %d", $time, a, b, eq, lt, gt);
          a=8'b11110000;
          b=8'b11110000;
      #10 a=8'b1001001;
          b=8'b10101010;
      #10 a=8'b11001100;
          b=8'b10101000;
      #10 $finish;
   end  
endmodule

我还在$完成后加了一个半。

Answer 2

我尝试了你的代码，唯一的问题是$ finish完成后缺少分号。所以＃10 $完成;

比较器的Verilog Testbench错误

2 个答案: