Question

我如何编写SVA来检查sig是否为高触发器在trigger [*4] |-> signal之前的4个周期内是高的不够好，因为它没有检查信号在3个周期内没有变高。我应该使用$past如何??

Answer 1

这将检查sig的上升沿，trigger是否高达4 clk周期：

assert_name: assert property (
   @(posedge clk) (
     ($rose(sig) -> $past(trigger,4))
   )
);

Answer 2

没有什么可以阻止你编写一小段可综合的RTL来计算trigger的周期数。{/ p>

always @(posedge clk) begin
    if (trigger) begin
        triggerCount := triggerCount + 1;
    end else begin
        triggerCount := 0;
    end
end

assert_name: assert property (
   @(posedge clk) (
     ($rose(sig) -> triggerCount == 4)
   )
);

system verilog assertion trigger == 1信号断言前的4个周期

2 个答案: