Question

我正在尝试编写一个只有当信号在＆＃39; clk＆＃39;的上升沿转换时才会触发的断言。我在下面写了代码来测试我的想法

module test();

bit clk, clkb;
int d;

assign clkb = ~clk;

initial begin
   clk = 0;
   forever #100 clk = ~clk;
end

initial begin
   d = 10;
   #150 d = 20;
end

sva_d_chgd: assert property (@(posedge clk) $stable(d,@(clkb))) 
   else $error($psprintf("err: time = %0d, clk = %b, d = %0d", $time, clk, d));

always @ (d or clk) begin
   $display("time = %0d, clk = %b, d = %0d", $time, clk, d);
   if ($time > 200) $finish;
end
endmodule

上面的代码在VCS中返回以下输出：

time = 0, clk = 0, d = 10
time = 100, clk = 1, d = 10
"test.vs", 18: test.sva_d_chgd: started at 100s failed at 100s
        Offending '$stable(d, @(clkb))'
Error: "test.vs", 18: test.sva_d_chgd: at time 100
err: time = 100, clk = 1, d = 10
time = 150, clk = 1, d = 20
time = 200, clk = 0, d = 20
time = 300, clk = 1, d = 20
$finish called from file "test.vs", line 23.
$finish at simulation time                  300

为什么断言会在时间100点开始，当时＆＃39; d＆＃39;保持稳定直到150年？

Answer 1

在你的代码中，在clk的每个posgege上进行稳定检查，以查看clkb的前两个边缘之间“d”的值是否发生了变化。因为在clk的第一个版本中，没有先前的clkb边缘值“d”，稳定返回“unknown”而不是“true”或“false”，这会导致你的断言失败。

我已经为你的代码添加了一个复位信号，并在第一次产生clk之前禁用了断言。当“d”发生变化时，我也感动了。

module test();

bit clk, clkb, rst;
int d;

assign clkb = ~clk;

initial begin
   clk = 0;
   forever #100 clk = ~clk;
end

initial begin
   rst = 1;
   #150 rst = 0;
end

initial begin
   d = 10;
   #250 d = 20;
end

sva_d_chgd: assert property (@(posedge clk)
                            disable iff (rst)
                            $stable(d,@(clkb))) 
   else $error($psprintf("err: time = %0d, clk = %b, d = %0d", $time, clk, d));

always @ (d or clk) begin
   $display("time = %0d, clk = %b, d = %0d", $time, clk, d);
   if ($time > 400) $finish;
end
endmodule

这是输出：

# time = 0, clk = 0, d = 10
# time = 100, clk = 1, d = 10
# time = 200, clk = 0, d = 10
# time = 250, clk = 0, d = 20
# time = 300, clk = 1, d = 20
# ** Error: err: time = 300, clk = 1, d = 20
#    Time: 300 ns Started: 300 ns  Scope: test.sva_d_chgd File: assert_test.sv Line: 26
# time = 400, clk = 0, d = 20
# time = 500, clk = 1, d = 20
# ** Note: $finish    : assert_test.sv(30)
#    Time: 500 ns  Iteration: 1  Instance: /test

这解决了断言的第一个意外失败，但我认为你编写断言的方式仍然没有实际捕获你正在寻找的条件。

Systemverilog断言检查不良信号转换

1 个答案: