SystemVerilog断言

时间:2017-02-27 14:53:11

标签: system-verilog assertions system-verilog-assertions

我有以下界面:

interface tx_in_interface (input bit clk, input bit tx_srstn);
   //dut input
   logic [15:0] xi;   
   logic [15:0] xq;   
   logic [15:0] sin;  
   logic [15:0] cos;  
   int  chind2;   
endinterface



interface tx_out_interface (input bit clk, input bit tx_srstn);
   //dut output
   logic [15:0] y;
   int chind2;   
endinterface

我想检查每次sin等于1(dec)y将是xi/sqrt(2),并且每次cos等于1(dec)y将是xq/sqrt(2)

我可以使用特定类型的systemVerilog断言(不使用记分板或覆盖率)吗?

2 个答案:

答案 0 :(得分:1)

是的我认为您可以简单地编写以下2个属性。

property sin_check;
  (sin == 'd1) |-> y == (xi/sqrt(2));
endproperty

property cos_check;
  (cos == 'd1) |-> y == (xq/sqrt(2));
endproperty

答案 1 :(得分:0)

以下2个断言可以验证您指定的条件:

//Creating instances of interface 
tx_in_interface tx_i; 
tx_out_interface tx_o;

//Checking conditions 
assert property (@posedge tx_i.clk) (tx_i.sin == 1) |-> tx_o.y == (tx_i.xi/sqrt(2)); 
else $error("Sine output error!");

assert property (@posedge tx_o.clk) (tx_i.cos == 1) |-> tx_o.y == (xq/sqrt(2)); 
else $error("Cos output error!");
Duolos的

SystemVerilog Assertions Tutorial是一个很好的资源。