Systemverilog在{＆lt;＆lt; {signal}}和{signal＆lt;＆lt;＆lt; 1}之间的位移差异？

Question

我有以下Vivado模拟器似乎不支持的代码（导致错误：[XSIM 43-3209] - Unsupported Construct）：

assign b = {<<{a}};

想知道我是否可以将此代码更改为以下内容：

assign b = a<<1;

有人可以确认上面的两行是否相同？ 请注意，a和b都是8位宽。谢谢！

Answer 1

No they are not the same. {<<{a}} is a bit reversal. Assuming a was declared with the range [7:0], you would need to write

assign b = {a[0],a[1],a[2],a[3],a[4],a[5],a[6],a[7]};