我正在尝试使用vivado的仿真工具来仿真Vivado的浮点IP内核。我的测试台如下:
`timescale 1ns / 1ps
module tb_test();
// input
reg sys_clk;
reg sys_rst_n;
// output
wire [63:0] dataa;
wire [63:0] datab;
wire [63:0] result;
wire res_valid;
initial begin
sys_clk = 1'b0;
sys_rst_n = 1'b0;
# 200
sys_rst_n = 1'b1;
end
always #10 sys_clk = ~sys_clk;
test u_test(
.sys_clk (sys_clk),
.sys_rst_n (sys_rst_n),
.dataa (dataa),
.datab (datab),
.dataa_valid(),
.datab_valid(),
.res_valid(res_valid),
.result (result)
);
endmodule
,模型测试如下:
//`timescale 1ns / 1ps
module test(
input sys_clk,
input sys_rst_n,
output reg [63:0] dataa,
output reg [63:0] datab,
output reg dataa_valid,
output reg datab_valid,
output reg res_valid,
output reg result
);
reg [9:0] cnt;
wire [63:0] data_result;
wire result_valid;
always @ (posedge sys_clk or negedge sys_rst_n)
begin
if(!sys_rst_n)
cnt <= 26'd0;
else if(cnt < 10'd1000)
cnt <= cnt + 1'b1;
else
cnt <= 10'd0;
end
always @(posedge sys_clk or negedge sys_rst_n)
begin
if (!sys_rst_n)
result <= 63'b0;
else if(cnt == 10'd300)
begin
dataa <= 63'H3FF0000000000000; // adder a
datab <= 63'H3FF0000000000000; // adder b
res_valid <= 63'H000000000000000000; // result
dataa_valid <= 1'b1;
datab_valid <= 1'b1;
end
else if(cnt == 10'd700)
begin
result <= data_result;
res_valid <= result_valid; //get result
end
else
result <= result;
end
add add (
.aclk(sys_clk), // input wire aclk
.s_axis_a_tvalid(dataa_valid), // input wire s_axis_a_tvalid
.s_axis_a_tdata(dataa), // input wire [63 : 0] s_axis_a_tdata
.s_axis_b_tvalid(datab_valid), // input wire s_axis_b_tvalid
.s_axis_b_tdata(datab), // input wire [63 : 0] s_axis_b_tdata
.m_axis_result_tvalid(result_valid), // output wire m_axis_result_tvalid
.m_axis_result_tdata(data_result) // output wire [63 : 0] m_axis_result_tdata
);
endmodule
计算结果为ZZZZZZZZZZZZZZZZ。你能告诉我我的测试台怎么了吗?
答案 0 :(得分:1)
我的模拟器向我发出了有关result
信号宽度不匹配的编译警告。您在测试平台中将其声明为64位,但在设计中仅声明为1位。假设您真的想要64位,请更改:
output reg result
收件人:
output reg [63:0] result