Question

我正在尝试使4位加法器具有进位和出位功能，但是当在下面的体系结构中将Sum和Cin求和时，我很难将Cin（进位）转换为std_logic_vector类型。您是否知道如何使这些类型合适，以便可以一起对它们进行算术运算？

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity four_bit_adder_simple is
        port(
                A, B : in std_logic_vector(3 downto 0);
                Cin : in std_logic;
                Sum : out std_logic_vector(3 downto 0);
                Cout : out std_logic);
end four_bit_adder_simple;

architecture unsigned_impl of four_bit_adder_simple is
    signal total : std_logic_vector(4 downto 0);
begin
        Sum <= std_logic_vector(resize(unsigned(A),5) + resize(unsigned(B),5));
        total <= Sum + Cin;
        Cout <= total(4);
end unsigned_impl;

编辑：这是我使Cout成为2位std_logic_vector的错误。应该只是一个简单的std_logic。

VHDL：将std_logic转换为std_logic_vector

0 个答案: